
Hyperstone E1-32X/E1-16X RISC/DSP
· 32-bit RISC/DSP processor
· Parallelism of ALU, DSP unit and
Load/Store unit
· 16, 32, 48-bit instructions
· 64 local, 26 global registers
· Local regs organized in circular
register stack with stack frames
· 4 GByte memory address space
· Separate I/O address space
· 8 kByte RAM on-chip (1 cycle)
· On-chip instruction cache
· Separate address and data bus
· 32-bit timer and watchdog timer
· Comprehensive DRAM controller
· Programmable bus timing for all
memory and I/O devices
· Clock frequency up to 80 MHz
· On-chip PLL (4:1)
· Static design
· 80 MIPS, up to 240 MOPS
· Up to 700 MIPS/Watt
· 1 k complex FFT in less than 0.5 ms
· 1 cycle MPY (16 x 16 bit)
· 4 cycle MPY (32 x 32 bit)
· 1 cycle multiply-add (pipelined)
· 1 cycle MOV, ADD, CMP SHIFT
· 1 cycle DRAM read or write (pipelined)
· Glue-less memory- and I/O-connection
· 80 mW @ 50 MHz power dissipation
· Fully automatic power-down mode
· Clock-off function
· Operating Voltage: 2.4V...5V
Compact architecture and high performance give
you a solid base for meeting or exceeding your
project requirements Hyperstone E1-32X/E1-16X
RISC/DSP
Compact design and low power consumption.
The Hyperstone's minimum transistor count results in
a low power consumption of about 80 mW at 50 MHz
(2.7 V) for the complete chip. An automatic power-
down reduces power consumption even further in
many applications. Due to the on-chip bus interface,
total power consumption depends on the external
load connected to the chip. The low power consumption
makes very small packages possible.
Various Types
The Hyperstone E1-32X RISC/DSP family is available
in various types. The external data bus-width is 32 bit
and 16 bit for the E1-32X and E1-16 series, respectively.
The package types for the E1-32X series are 144-pin
TQFP (20 x 20 x 1.4mm) and 160-pin PQFP
(28 x 28 x 3.4mm), whereas the E1-16X series comes
in a very compact (14 x 14 x 1.4mm) 100-pin TQFP
package. Each type has 8 kByte on-chip RAM and
maximum clock rates of up to 80 MHz.
Hyperstone
RISC/DSP
CPU
DSP
Memory
Peripherals
Glue logic
decoders
latches
memory control
I/O control etc.
Memory
DRAM
EDO RAM
(Flash-)EPROM
SRAM
Peripherals
no glue logic
Hyperstone Architecture