- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369586 > RH8053GC021512 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | RH8053GC021512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 17/81頁 |
| 文件大?。?/td> | 598K |
| 代理商： | RH8053GC021512 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
17
2.3
GTL+ Signals
The mobile Intel Celeron processor system bus signals use a variation of the low-voltage swing
GTL signaling technology. The mobile Intel Celeron processor system bus specification is similar
to the Pentium II processor system bus specification, which is a version of GTL with enhanced
noise margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Intel Celeron processor.
The GTL+ system bus of the Celeron processor was designed to support high-speed data transfers
with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are
short. It is possible to change the layout and termination of the system bus to take advantage of the
mobile environment using the same GTL+ I/O buffers. In mobile systems the GTL+ system bus is
terminated at one end only. This termination is provided on the processor core (except for the
RESET# signal). Refer to the
Mobile Pentium
III
Processor GTL+ System Bus Layout Guideline
for details on laying out the GTL+ system bus.
2.4
Mobile Intel Celeron Processor CPUID
After a power-on RESET or when the CPUID version information is loaded, register EAX and
EBX[7:0] contains the values shown in Table 4. After the L2 cache is initialized, the CPUID
cache/TLB descriptors will be the values shown in Table 5.
Table 4. Mobile Intel Celeron Processor CPUID
EAX[31:0]
EBX[7:0]
Reserved [31:14]
Type [13:12]
Family [11:8]
Model [7:4]
Stepping [3:0]
Brand ID
X
0
6
8
X
01
Table 5. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 41H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RH8053GC025512 | Microprocessor |
| RH8053GC029512 | Microprocessor |
| RH8053GC033512 | Microprocessor |
| BXYP14 | BXYP14 - Waraktor |
| BXYP26 | Octal D-type flip flop with clear |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RH80554RC009512 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| RH80554RC021512 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
| RH9711 | 制造商:Thomas & Betts 功能描述:Ring Tongue Terminal 54.35mm 19.55mm Electro-Tin |
| RH9731 | 制造商:Thomas & Betts 功能描述:Ring Tongue Terminal 54.35mm 19.55mm Electro-Tin |
| RH9731U | 制造商:Thomas & Betts 功能描述:Ring Tongue Terminal 54.35mm 19.55mm Electro-Tin |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。