參數(shù)資料
型號: RG82845MZ
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 134/157頁
文件大?。?/td> 1407K
代理商: RG82845MZ
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
78
Datasheet
250687-002
R
3.7.32.
LPTT – AGP Low Priority Transaction Timer Register – Device
#0
Address Offset:
BDh
Default Value:
00h
Access:
Read/Write, Read Only
Size:
8 bits
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum
tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SBA
mechanisms.
The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66
necessarily apply to a single transaction, but can span multiple low-priority transactions of the same type.
After this time expires the AGP arbiter may grant the bus to another agent if there is a pending request.
The LPTT does not apply in the case of high-priority request where ownership is transferred directly to
high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT
value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h,
then the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.
Bit
Description
7:3
Low Priority Transaction Timer Count Value (LPTTC): The number of clocks programmed in these
bits represents the guaranteed time slice (measured in eight 66-MHz clock granularity) allotted to the
current low priority AGP transaction data transfer state.
2:0
Reserved
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