參數(shù)資料
型號： RG82845MP
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 106/157頁
文件大?。?/td> 1407K
代理商： RG82845MP
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
52
Datasheet
250687-002
R
3.7.3.
PCICMD – PCI Command Register – Device #0
Address Offset:
04-05h
Default:
0006h
Access:
Read/Write, Read Only
Size
16 bits
Since MCH-M Device #0 does not physically reside on PCI0 many of the bits are not implemented.
Bit
Descriptions
15:10
Reserved
9
Fast Back-to-Back Enable (RO). This bit controls whether or not the master can do fast back-to-
back writes to different targets. Since device #0 is strictly a target this bit is not implemented and is
hardwired to 0. Writes to this bit position have no effect.
8
SERR Enable (SERRE) (R/W). This bit is a global enable bit for Device #0 SERR messaging. The
MCH-M does not have an SERR# signal. The MCH-M communicates the SERR# condition by
sending an SERR message to the ICH3-M. If this bit is set to a 1, the MCH-M is enabled to generate
SERR messages over hub interface for specific Device #0 error conditions that are individually
enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers.
If SERRE is reset to 0, then the SERR message is not generated by the MCH-M for Device #0.
NOTE: This bit only controls SERR message for the Device #0. Device 1 has its own SERRE bits to
control error reporting for error conditions occurring on their respective devices.
7
Address/Data Stepping (RO). Address/data stepping is not implemented in the MCH-M, and this bit
is hardwired to 0. Writes to this bit position have no effect.
6
Parity Error Enable (PERRE) (R/W). PERR# is not implemented by the MCH-M, and this bit is
hardwired to 0. Writes to this bit position have no effect.
5
VGA Palette Snoop (RO). The MCH-M does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
4
Memory Write and Invalidate Enable(MWIE) (RO). The MCH-M does not implement this bit and it
is hardwired to a 0. Writes to this bit position have no effect.
3
Special Cycle Enable(SCE) (RO). The MCH-M does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
2
Bus Master Enable (BME) (RO). The MCH-M is always enabled as a master on hub interface A.
This bit is hardwired to a “1”. Writes to this bit position have no effect.
1
Memory Access Enable (MAE) (RO). The MCH-M always allows access to main memory. This bit
is not implemented and is hardwired to 1. Writes to this bit position have no effect.
0
I/O Access Enable (IOAE) (RO). This bit is not implemented in the MCH-M and is hardwired to a 0.
Writes to this bit position have no effect.
相關(guān)PDF資料
PDF描述
RG82845MZ Controller Miscellaneous - Datasheet Reference
RG82870P2 Controller Miscellaneous - Datasheet Reference
RH5RE36AA-T1-FA 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RH5RE56AA-T1-FA 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RE5RE36AA-TZ-FC 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RG82845MP S L66J 制造商:Intel 功能描述:Chipset Memory Controller Hub Mobile 593-Pin FCBGA
RG82845MZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference
RG82845PE S L6H5 制造商:Intel 功能描述:CHIPSTGMCH 82845PE HT-PBGA760
RG82845PESL6Q3 制造商:Intel 功能描述:Chipsets
RG82845-SL5V7 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*