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參數(shù)資料
| 型號(hào)： | RF2968 |
| 廠商： | RF MICRO DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | BLUETOOTHTM TRANSCEIVER |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | RF2968 |
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Preliminary
11-122
RF2968
Rev A13 010912
11
T
Pin
17
Function
BRCLK
Description
Reference clock output. This is a crystal controlled reference clock in
the 10-40MHz range, typically 13MHz.
Interface Schematic
18
19
OSC O
OSC I
Same as pin 19.
See pin 19.
The OSC pins are used to produce the reference frequency by means
of negative feedback. A crystal and resistor are placed in parallel from
OSC I to OSC O to provide the feedback path and establish the reso-
nant frequency. A shunt capacitor is placed on each OSC pin to provide
the proper loading of the crystal. If an external reference is used, it is
connected to OSC I through a DC-blocking capacitor, and OSC O is
connected to OSC I through a 470k
resistor.
Latches data entered into the serial port. Data is clocked into the latch
on the rising edge of BnDEN.
Serial data port. Read/write data is sent through this pin into / out of the
on chip shift register. Read data is transferred on the rising edge of
BDCLK. Write data is transferred on the falling edge of BDCLK.
Serial port input clock.This pin is used to clock data into the serial port.
To minimize the hop frequency programming time, a BDCLK frequency
of 10-20MHz is recommended.
This pin is part of the chip power control circuit. It is used to power up
the chip from the “off” state.
20
BnDEN
See pin 23.
21
BDDATA
22
BDCLK
See pin 23.
23
BnPWR
24
PLL GND
Ground connection for the RF synthesizer, crystal oscillator, and serial
port.
Supply voltage for the RF synthesizer, crystal oscillator, and serial port.
25
26
VCC6
D0
This is the output of the charge pump for the RF PLL. An RC network
from this pin to ground is used to establish the PLL bandwidth. To mini-
mize synthesizer settling time and phase noise, a dual loop bandwidth
scheme is implemented. During the initial period of frequency acquisi-
tion, a wide loop bandwidth is used. RSHUNT is used to switch to a
narrow loop bandwidth near the end of the frequency acquisition, pro-
viding improved VCO phase noise. The time at which the bandwidth
switches is set by the PLLDel bits.
27
RSHUNT
Switches the loop filter from wide to narrow bandwidth by shunting the
midpoint of two external series resistors to ground.
The RESNTR pins are used to supply DC voltage to the VCO as well
as to tune the center frequency of the VCO. Two inductors are required
between RESNTR- and RESNTR+ to resonate with the internal capac-
itance. Inductance of traces from the RESNTR pins to the inductor
should be taken into account in the board layout.
28
RESNTR-
V
CC
BRCLK
OSC O
OSC I
READ DATA
WRITE DATA
Pin 21
BnPWR
V
CC
D0
V
CC
RESNTR-
RESNTR+
D0
4 k
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