參數資料
型號: RF24
英文描述: Analog IC
中文描述: 模擬IC
文件頁數: 3/6頁
文件大?。?/td> 227K
代理商: RF24
6-3
RF2456
Rev B5 001002
6
M
Pin
1
Function
VCC
Description
Supply Voltage for the mixers, bias circuits, and control logic. External
RF and IF bypassing is required. The trace length between the pin and
the bypass capacitors should be minimized. The ground side of the
bypass capacitors should connect immediately to ground plane.
Interface Schematic
2
IF2-
Same as pin 3, except complimentary output. For typical single ended
operation, this pin is connected directly to V
CC
.
FM IF Output pin. This is a balanced output, but is typically used as a
single-ended output. The internal circuitry, in conjunction with an exter-
nal matching/bias inductor to V
CC
, sets the operating impedance. This
inductor is typically incorporated in the matching network between the
output and IF filter. The net output impedance, including the external
inductor, is about 870
at 85MHz. Because this pin is biased to V
CC
, a
DC blocking capacitor must be used if the IF filter input has a DC path
to ground. See Application Schematic.
Ground connection. Keep traces physically short and connect immedi-
ately to ground plane for best performance.
CDMA IF Output pin. This is a balanced output. The internal circuitry, in
conjunction with an external matching/bias inductor to V
CC
, sets the
operating impedance. This inductor is typically incorporated in the
matching network between the output and IF filter. The net output
impedance, including the external inductor, at 85MHz is higher than
1k
, even though the part is designed to drive a 1k
load. Because
this pin is biased to V
CC
, a DC blocking capacitor must be used if the IF
filter input has a DC path to ground. See Application Schematic.
Same as pin 5, except complementary output.
See pin 3.
3
IF2+
4
GND
5
IF 1+
6
7
IF 1-
See pin 5.
IF SELECT
Control line for IF out select. A logic “l(fā)ow” enables the FM output. A
logic “high” enables the CDMA output. The threshold voltage is 1.6V,
and the pin draws less than 50
μ
A when selected.
8
PD
Power down pin. A logic “l(fā)ow” turns the part off. A logic “high” (>1.6V)
turns the part on. In addition, pin 7 (IF SELECT) should also be taken
low during power down.
9
LO IN+
Mixer LO Balanced Input Pin. For single-ended input operation, this pin
is used as an input and pin 10 is bypassed to ground.
10
11
LO IN-
GND
Same as pin 9 except complementary input.
See pin 9.
Ground connection for the mixer. Keep traces physically short and con-
nect immediately to ground plane for best performance.
Mixer RF Input Pin. This pin is internally DC biased and should be DC
blocked if connected to a device with DC present. External matching
network sets RF and IF impedance for optimum performance.
12
MIX IN
13
BYP
Internal voltage reference. External RF and IF bypassing is required.
The trace length between the pin and the bypass capacitors should be
minimized. The ground side of the bypass capacitors should connect
immediately to ground plane.
Same as pin 4.
14
15
16
GND
GND
GND
Same as pin 4.
Same as pin 4.
LO OUT
VCC2
BIAS
IF2-
IF2+
2.1 k
8.5 pF
IF1-
IF1+
1.2
pF
1.2
pF
GND2
C1
50 k
PD
50 k
LO IN+
LO IN-
MIX IN
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