參數(shù)資料
型號: RF2186PCBA
廠商: RF Micro Devices, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: 3V W-CDMA POWER 1900MHZ/ 3V LINEAR POWER AMPLIFIER
中文描述: 3V的的W - CDMA功率1900MHZ / 3V的線性功率放大器
文件頁數(shù): 3/6頁
文件大?。?/td> 155K
代理商: RF2186PCBA
Preliminary
2-199
RF2186
Rev A2 010515
2
P
Pin
1
Function
GND1
Description
Ground for first stage. For best performance, keep traces physically
short and connect immediately to ground plane. This ground should be
isolated from the backside ground contact.
Power Down control for first and second stages. When this pin is “l(fā)ow”,
all first and second stage circuits are shut off. When this pin is 2.8V, all
first and second stage circuits operate normally. V
PD1
requires a regu-
lated 2.8V for the amplifier to operate properly over all specified tem-
perature and voltage ranges. A dropping resistor from a higher
regulated voltage may be used to provide the required 2.8V.
V
MODE
adjusts the bias to the second and third stages. In normal oper-
ation and for maximum efficiency, V
MODE
should be “high”. In this mode
the power and linearity will meet the published specifications. If addi-
tional linearity is desired, V
MODE
may be pulled “l(fā)ow”, however effi-
ciency will decrease. If V
MODE
is pulled “l(fā)ow”, the output match will
need to be adjusted for optimum performance.
Power Down control for third stage. When this pin is “l(fā)ow”, all third
stage circuits are shut off. When this pin is 2.8V, all third stage circuits
operate normally. V
PD
requires a regulated 2.8V for the amplifier to
operate properly over all specified temperature and voltage ranges. A
dropping resistor from a higher regulated voltage may be used to pro-
vide the required 2.8V. A 15pF high frequency bypass capacitor is rec-
ommended.
For best performance, keep traces physically short and connect to
ground plane through a 15nH inductor. This ground should be isolated
from the backside ground contact.
Not Connected.
Interface Schematic
See pin 16.
2
VPD1
3
VMODE
4
VPD2
5
BIAS GND
6
7
NC
RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the third stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1920MHz to 1980MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass-
ing is required for stability.
Same as pin 7.
8
9
RF OUT
2FO
See pin 7.
Second harmonic trap. Keep traces physically short and connect imme-
diately to ground plane. This ground should be isolated from backside
ground contact.
Supply for bias reference and control circuits. High frequency bypass-
ing may be necessary.
Power supply for second stage and interstage match. Pins 11 and 12
should be connected by a common trace where the pins contact the
printed circuit board.
Same as pin 11.
10
VCC
11
VCC2
12
13
14
15
VCC2
NC
NC
VCC1
Not Connected.
Not Connected.
Power supply for first stage and interstage match. V
CC
should be fed
through a 1.2nH inductor terminated with a 8.2pF capacitor on the sup-
ply side. The inductor should be as close to the pin as possible.
RF input. An external series capacitor is required as a DC block.
See pin 16.
16
RF IN
Pkg
Base
GND
Ground connection. The backside of the package should be soldered
to a top side ground pad which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.
RF OUT
From Bias
Network
GND1
RF IN
VCC1
From Bias
Network
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