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參數(shù)資料
| 型號： | RF2153PCBA |
| 廠商： | RF Micro Devices, Inc. |
| 英文描述： | CDMA/TDMA/PACS 1900MHZ 3V POWER AMPLIFIER |
| 中文描述： | 碼分多址/時分多址/ PACS系統(tǒng)1900MHZ 3V的功率放大器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 287K |
| 代理商： | RF2153PCBA |
2-170
RF2153
Rev A18 001114
2
P
Pin
1
Function
VCC2
Description
Power supply for second stage and interstage match. Pins 1, 15 and 16
should be connected by a common trace where the pins contact the
printed circuit board.
Ground for second stage. Keep traces physically short and connect
immediately to ground plane for best performance. This ground should
be isolated from the backside ground contact on top metal layer.
Power supply for first stage and interstage match. V
CC
should be fed
through a 1.5nH inductor terminated with a 15pF capacitor on the sup-
ply side.
RF input. An external 15pF series capacitor is required as a DC block
and also provides for an input VSWR of <2:1 typical.
Interface Schematic
2
GND2
3
VCC1
See pin 4.
4
RF IN
5
GND1
Ground for first stage. Keep traces physically short and connect imme-
diately to ground plane for best performance. This ground should be
isolated from the backside ground contact on top metal layer.
Power Down control for first and second stages. When this pin is “l(fā)ow”,
all first and second stage circuits are shut off. When this pin is 2.8V, all
first stage circuits are operating normally. V
PD1
requires a regulated
2.8V for the amplifier to operate properly over all specified temperature
and voltage ranges. A dropping resistor from a higher regulated voltage
may be used to provide the required 2.8V.
For full power operation, MODE is set low. VMODE will reduce the bias
current by up to 50% when set HIGH. Large Signal Gain is reduced
approximately 1.5dB at 29dBm P
OUT
and Small Signal Gain is reduced
approximately 6dB. An external series resistor is optional to limit the
amount of current required by the V
MODE
pin.
Power Down control for the third stage. When this pin is “l(fā)ow”, the third
stage circuit is shut off. When this pin is 2.8V, the third stage circuit is
operating normally. V
PD
requires a regulated 2.8V for the amplifier to
operate properly over all specified temperature and voltage ranges. A
dropping resistor from a higher regulated voltage may be used to pro-
vide the required 2.8V. A 15pF high frequency bypass capacitor is rec-
ommended.
Requires a 15nH inductor.
See pin 4.
6
VPD1
7
VMODE
8
VPD2
9
10
BIAS GND
RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the third stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1850MHz to 1910MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass-
ing is required for stability.
Same as pin 12.
11
12
13
RF OUT
RF OUT
2FO
See pin 10.
Same as pin 12.
See pin 10.
Second harmonic trap. Keep traces physically short and connect imme-
diately to ground plane. This ground should be isolated from backside
ground contact.
Supply for bias reference and control circuits. High frequency bypass-
ing may be necessary.
Same as pin 1.
14
VCC
15
16
Pkg
Base
VCC2
VCC2
GND
Same as pin 1.
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
GND1
RF IN
VCC1
From Bias
Network
RF OUT
From Bias
Network
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