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參數(shù)資料
| 型號(hào)： | RD28F3204W30B85 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA80 |
| 封裝： | 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80 |
| 文件頁數(shù)： | 20/82頁 |
| 文件大小： | 749K |
| 代理商： | RD28F3204W30B85 |
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28F6408W30, 28F3204W30, 28F320W30, 28F640W30
14
Preliminary
.
4.2.1
Read Mode (RM)
CR.15 sets the flash read mode. The two read modes are page mode (default mode) and burst
mode. The flash device can only be configured for one of these modes at any one time.
4.2.2
First Latency Count (LC
2
–
0
)
The First Access Latency Count configuration tells the device how many clocks must elapse from
ADV#-high (V
IH
) before the first data word should be driven onto its data pins. The input clock
frequency determines this value. See
Table 6,
“
Configuration Register Bits
”
on page 13
for latency
values.
Figure 7,
“
First Access Latency Configuration
”
on page 16
shows data output latency from
ADV#-active for different latencies.
Use these equations to calculate First Access Latency Count:
{1/ Frequency} = CLK Period
(1)
n (CLK Period)
≥
t
AVQV
(ns) + t
ADD-DELAY
(ns) + t
DATA
(ns) (2)
n-2 = First Access Latency Count (LC)
*
(3)
Table 7. Configuration Register Bit Settings
Bit Name
Setting
Read Mode (RM)
CR.15
0 = Burst or synchronous mode.
1 = Page or asynchronous mode.
First Latency Count (LC
2-0
)
CR.13
–
CR.11
Code 0 = 000. Reserved.
Code 1 = 001. Reserved.
Code 2 = 010.
Code 3 = 011.
Code 4 = 100.
Code 5 = 101.
Code 6 = 110. Reserved.
Code 7 = 111. Reserved.
WAIT Polarity (WT)
CR.10
0 = active low signal.
1 = active high signal
Data Output Configuration (DOC)
CR.9
0 = hold data for one clock cycle.
1 = hold data for two clock cycles.
WAIT Configuration (WC)
CR.8
0 = WAIT signal asserted during 16-word row boundary transition.
1 = WAIT signal assert one data cycle before 16-word row boundary
transition.
Burst Sequence (BS)
CR.7
0 = Intel burst sequence.
1 = linear burst sequence.
Clock Configuration (CC)
CR.6
0 = falling edge of clock.
1 = rising edge of clock.
Burst Wrap (BW) CR.3
0 = Wrap enabled.
1 = Wrap disabled.
Burst Length (BL
2-0
)
CR.2
–
CR.0
001 = 4 Word burst mode.
010 = 8 Word burst mode.
011 = Reserved.
111 = Continuous burst mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RD28F3204W30T70 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| RD28F3204W30T85 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| RD28F6408W30B70 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| RD28F6408W30B85 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| RD28F6408W30T70 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RD28F3204W30T70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| RD28F3204W30T85 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| RD28F3208C3B70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 VOLT INTEL Advanced+ Boot Block Flash Memory (C3) Stacked-Chip ScalPackage Familye |
| RD28F3208C3B90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 VOLT INTEL Advanced+ Boot Block Flash Memory (C3) Stacked-Chip ScalPackage Familye |
| RD28F3208C3T70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 VOLT INTEL Advanced+ Boot Block Flash Memory (C3) Stacked-Chip ScalPackage Familye |
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