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參數(shù)資料
| 型號： | RD-19230F-202T |
| 英文描述： | Converter |
| 中文描述： | 轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 152K |
| 代理商： | RD-19230F-202T |
13
Data Device Corporation
www.ddc-web.com
RD-19230
DATA
DATA
VALID
150 nsec max
INHIBIT
100 nsec MAX
ENABLE
150 nsec MAX
DATA
DATA
VALID
HIGH Z
HIGH Z
250 to 750 nsec
CB
50 nsec
DATA
DATA
VALID
DATA
VALID
FIGURE 18. INHIBIT TIMING
FIGURE 19. ENABLE TIMING
FIGURE 20. CONVERTER BUSY TIMING
1) Tie UP/DN to pin -5V.
2) Choose the two bandwidths following the guidelines in the
General Setup Considerations; the R
V
resistor must be the same
value for both bandwidths.
3) Use the SHIFT pin to choose between bandwidths. A logic 1
selects the VEL1 components and a logic 0 selects the VEL2
components.
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 18,
angular output data is valid 150 ns maximum after the applica-
tion of the negative inhibit pulse.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 19, output data is valid 150 ns maximum after
the application of a negative enable pulse.The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 20,
output data is valid 50 nS maximum after the middle of the CB
pulse. CB pulse width is 1/40 F
S
, which is nominally 375 ns.
INTERNAL ENCODER EMULATION
The RD-19230 can be programmed to encoder emulation mode
by connecting the A_QUAD_B input to GND. The U/B output pin
becomes B (LSB XOR LSB + 1). The A (LSB + 1) and B output
signals can be used in control systems that are designed to inter-
face with incremental optical encoders. To enable the Zero Index
pulse, ZIP_EN should be tied to GND.
The resolution of the incremental outputs is latched from the D0
and D1 inputs on the low going edge of A_QUAD_B.The resolu-
tion of the parallel data outputs may be changed any time after
the encoder resolution is latched (see FIGURE 23, on page 14).
Note:The encoder resolution must be less than or equal to
the resolution of the parallel data outputs. Refer to
FIGURE 21.
The timing of the A, B and ZIP (or North Reference Pole [NRP])
output is dependent on the rate of change of the
synchro/resolver position (rps or degrees per second) and the
encoder resolution latched into the RD-19230 (refer to
FIGURE 22).The calculations for the timing are:
n = encoder resolution latched into RD-19230
t = 1 / ( 2
n
* Velocity(RPS))
T = 1 / ( Velocity(RPS))
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RD-19230F-203T | Converter |
| RD-19230F-302T | Converter |
| RD-19230F-303T | Converter |
| RD-19230FX-202 | Resolver-to-Digital Converter |
| RD-19230FX-202T | Resolver-to-Digital Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RD-19230F-203T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter |
| RD-19230F-302T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter |
| RD-19230F-303T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter |
| RD-19230FX-202 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-202T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Resolver-to-Digital Converter |
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