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PRODUCT SPECIFICATION
RC5050
9
When S1 opens, the diode D1 will conduct the inductor cur-
rent and the output current will be delivered to the load
according to the equation:
where T
S
is the overall switching period and (T
S
– T
ON
) is
the time during which S1 is open.
By solving these two equations, we can arrive at the basic
relationship for the output voltage of a step-down converter:
In order to obtain a more accurate approximation for V
OUT
,
we must also include the forward voltage V
D
across diode
D1 and the switching loss, Vsw. After taking into account
these factors, the new relationship becomes:
where V
SW
= MOSFET switching loss
= I
L
R
DS,ON
The RC5050 Controller
The RC5050 is a programmable DC-DC controller IC. When
designed around the appropriate external components, The
RC5050 can be configured to deliver more than 14.5A of
output current. The RC5050 utilizes both current-mode and
voltage-mode control to create an integrated step-down volt-
age regulator. During heavy loading conditions, the RC5050
functions as a PWM step down regulator. Under light loads,
the controller goes into Pulse Frequency Modulation (PFM)
or pulse-skipping mode. The controller will sense the load
level and switch between the two modes automatically, thus
optimizing its efficiency under all conditions.
Main Control Loop
For this discussion, refer to the Block Diagram on page 1 of
the data sheet. The control loop of the regulator contains two
main sections; the analog control block and the digital con-
trol block. The analog block consists of signal conditioning
amplifiers feeding into a set of comparators which provide
the inputs to the digital block. The signal conditioning sec-
tion accepts inputs from the IFB (current feedback) and VFB
(voltage feedback) pins and sets up two controlling signal
paths. The voltage control path amplifies the VFB signal and
presents the output to one of the summing amplifier inputs.
The current control path takes the difference between the
IFB and VFB pins and presents the resulting signal to
another input of the summing amplifier. These two signals
are then summed together with the slope compensation input
from the oscillator. This output is then presented to a com-
parator, which provides the main PWM control signal to the
digital control block.
The additional comparators in the analog control section set
the point at which the max current comparator disables the
output drive signals to the external power MOSFETs.
The digital control block is designed to take the comparator
inputs along with the main clock signal from the oscillator
and provide the appropriate pulses to the HIDRV output pin
that controls the external power MOSFET(s). The digital
section was designed utilizing high speed Schottky transistor
logic, thus allowing the RC5050 to operate at clock speeds
as high as 1MHz.
High Current Output Drivers
The RC5050 contains a high current output driver which uti-
lizes high speed bipolar transistors arranged in a push-pull
configuration. This driver is capable of delivering 1A of cur-
rent in less than 100ns. The driver's power and ground are
separated from the overall chip power and ground for addi-
tional switching noise immunity. The output driver power
supply, VCCQP, is derived from an external 12V supply
through a 47
W
series resistor. The resulting voltage is suffi-
cient to provide the gate-source voltage to the external MOS-
FET required in order to achieve a low R
DS,ON
.
Internal Voltage Reference
The reference included in the RC5050 is a precision band-
gap voltage reference. The internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Added to the reference output is the resulting output from an
integrated 5-bit DAC. The DAC is provided in order to allow
the DC-DC converter output to be directly programmable via
a 5-bit digital input. When the VID4 pin is in the HIGH state,
pins VID3–VID0 will scale the output voltage from 2V to
3.5V in 100mV increments. When the VID4 pin is pulled
LOW, the output can be programmed from 1.3V to 2.05V in
50mV steps. For guaranteed stable operation under all oper-
ating conditions, a 0.1
m
F decoupling capacitor should be
connected to the VREF pin. No load should be imposed upon
this pin.
Power Good (PWRGD)
The RC5050 Power Good function is designed in accordance
with the Pentium II DC-DC converter specifications and pro-
vides a constant voltage monitor on the VFB pin. The inter-
nal circuitry compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
the power supply voltage exceed
±
10% of its nominal set-
point. The Power Good flag provides no other control func-
tion to the RC5050.
Output Enable (ENABLE)
Intel specifications state that the DC-DC converter should
accept an open collector signal for controlling the output
voltage; a logic LOW on the ENABLE pin disables the out-
put voltage. When disabled, the PWRGD output is in the
low state.
I
L
V
T
-------------------------------------------
T
–
(
)
L1
=
V
OUT
V
IN
T
T
S
----------
è
=
V
OUT
V
IN
V
D
V
SW
–
+
(
)
T
T
S
----------
V
D
–
=