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PRODUCT SPECIFICATION
RC7104
9
Figure 1. Input Logic Selection through Resistor Load Option
Figure 2. Input Logic Selection through Jumper Option
Serial Data Interface
The RC7104 features a two-pin, serial data interface that can be used to configure internal register settings that control particular
device functions. Upon power-up, the RC7104 initializes with default register settings. Therefore, the use of this serial data
interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset.
RC7104
OUTPUT
BUFFER
10k
(LOAD
OPTION 0)
CLOCK
LOAD
10k
(LOAD
OPTION 1)
VDD
OUTPUT
STRAPPING
RESISTOR
SERIES
TERMINATION
RESISTOR
RC7104
OUTPUT
BUFFER
CLOCK
LOAD
10k
JUMPER
OPTIONS
OUTPUT
STRAPPING
RESISTOR
SERIES
TERMINATION
RESISTOR
RESISTOR
VALUE R
R
Functional Description
I/O Pin Operation
Pin 27 is a dual purpose l/O pin. The RC7104 upon power
up, the first 2ms of operation is used for input logic selection,
(allowing the determination of assigned device functions).
During this period, the 48MHz clock output buffer is tristated,
allowing the output strapping resistor on the l/O pin to pull the
pin and its associated capacitive clock load to either a logic
high or low state. At the end of the 2ms period, the estab-
lished logic “0” or “1” condition of the l/O pin is then latched.
Next the output buffer is enabled which converts the l/O pin
into an operating clock output. The 2ms timer is started when
VDD reaches 2.0V. The input bits can only be re-set by turn-
ing VDD off and then back on again. (This feature reduces
device pin count by combining clock outputs with input
select pins.)
It should be noted that the strapping resistors have no significant
effect on clock output signal integrity. The drive impedance
of clock output is 20 ohms (nominal) which is minimally
affected by the 10 kohm strap to ground or VDD. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
An external 10 kohm “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a “0”
bit, connection to VDD sets a “1” bit. Figure 1 and Figure 2
show two suggested methods for strapping resistor connections.