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RC7104
PRODUCT SPECIFICATION
6
A
AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C; VDDREF = VDDPCI = VDD48MHz = 3.3V
±
5%; VDDAPIC = VDDCPU = 2.5V
±
5%;
f
XTL
= 14.31818MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz
Min.
Typ. Max. Min.
15
5.2
5.0
.4
.4
45
CPU = 100MHz
Typ. Max.
10
3.0
2.8
.4
.4
45
Units
ns
ns
ns
ns
ns
%
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
Test Condition/Comments
Measured on rising edge at 1.25.
Duration of clock cycle above 2.0V.
Duration of clock cycle below 0.4V.
Measured from 0.4V to 2.0V.
Measured from 2.0V to 0.4V.
Measured on rising and falling
edge at 1.25V.
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
Measured on rising edge at 1.25V.
Assumes full supply voltage
reached within 1ms from power-
up.
Average value during switching
transition. Used for determining
series termination value.
Period
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
15.5
10.5
1.6
1.6
55
1.6
1.6
55
t
JC
Jitter, Cycle-to-Cycle
200
200
ps
t
SK
f
ST
Output Skew
Frequency Stabilization
from Power-up
(cold start)
AC Output Impedance
175
3
175
3
ps
ms
Z
0
20
20
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30pF)
CPU = 66.6/100MHz
Min.
Typ.
30
12.0
Units
ns
ns
Parameter
t
P
t
H
Max.
Test Condition/Comments
Measured on rising edge at 1.5V.
Duration of clock cycle above
2.4V.
Duration of clock cycle below
0.4V.
Measured from 0.4V to 2.4V.
Measured from 2.4V to 0.4V.
Measured on rising and falling
edge at 1.5V.
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
Measured on rising edge at 1.5V.
Covers all CPU/PCI outputs.
Measured on rising edge at 1.5V.
CPU leads PCI output.
Period
High Time
t
L
Low Time
12.0
ns
t
R
t
F
t
D
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
1
4
4
V/ns
V/ns
%
45
55
t
JC
Jitter, Cycle-to-Cycle
250
ps
t
SK
t
O
Output Skew
CPU to PCI Clock Offset
500
4.0
ps
ns
1.5