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RC7100
PRODUCT SPECIFICATION
2
A
crystal. The REF and IOAPIC clocks are generated directly
from the reference frequency.
The PWRDWN# pin when low powers down the crystal
oscillator and the two phase locked loops. Other pins to
control power are the CPUSTOP# and PCISTOP#.
The CPUSTOP# when low causes the CPU clocks to go to a
low state. The PCISTOP# when low causes the PCI clocks
with the exception of the PCICLK_F to go to a low state.
The PCICLK_F is a free-running clock. All clock outputs
will be tristated when SEL0, SEL1 and SEL100/66# are all
low.
Frequency selection between 100 MHz and 66 MHz can be
accomplished with the SEL100/66#. SEL100/66# high will
provide the 100 MHz operation and low will provide a clock
frequency of 66 MHz. Additional frequency selections
including TEST MODE can be had with other combinations
of the SEL0 and SEL1 pins. See Table 1 for more details.
Spread Spectrum clocking is available for the CPU and PCI
clocks. It can be activated by bringing the SPREAD# pin to a
low state. the REF, IOAPIC and 48MHz clocks are not
affected by the SPREAD#.
Table 1. Selectable Modes
Pin Assignments
SEL0
0
1
0
1
0
1
0
1
SEL 1
0
0
1
1
0
0
1
1
SEL100/66
0
0
0
0
1
1
1
1
CPU
HI-Z
75
75
66
TC/2
83.3
83.3
100
PCI
HI-Z
37.5
30
33
TC/6
41.65
33.3
33
REF
HI-Z
14.318
14.318
14.318
TC/2
14.318
14.318
14.318
IOAPIC
HI-Z
14.318
14.318
14.318
TC
14.318
14.318
14.318
48
HI-Z
48
48
48
TC
48
48
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
SEL100/66#
SEL1
SEL0
SPREAD#
PWRDWN#
CPUSTOP#
PCISTOP#
VSScore
VDDcore
VSScpu
CPUCLK3
CPUCLK2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0
REF1
VSSref
XTALIN
XTALOUT
VSSpci
PCICLKF
PCICLK0
VDDpci
PCICLK1
PCICLK2
VSSpci
Pin # Pin Name
Pin # Pin Name
Pin # Pin Name
Pin # Pin Name
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PCICLK3
PCICLK4
VDDpci
PCICLK5
PCICLK6
VSSpci
VDDcore
VSScore
VDD48MHz
48MHz0
48MHz1
VSS48MHz
VDDcpu
VSScpu
CPUCLK1
CPUCLK0
VDDcpu
NC
VSSapic
APIC1
APIC0
VDDapic
REF2
VDDref
Description
(continued)