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參數(shù)資料
| 型號(hào)： | RC5061 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms |
| 中文描述： | 高性能可編程同步DC - DC控制器的多電壓平臺(tái) |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 135K |
| 代理商： | RC5061 |
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PRODUCT SPECIFICATION
RC5061
REV. 1.0.0 7/6/00
13
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhancement
Mode Field Effect Transistors. Desired characteristics are as
follows:
Low Static Drain-Source On-Resistance, R
DS,ON
< 20m
(lower is better)
Low gate drive voltage, V
GS
= 4.5V rated
Power package with low Thermal Resistance
Drain-Source voltage rating > 15V.
The on-resistance (R
DS,ON)
is the primary parameter for
MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8.
Inductor Selection
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize ripple
or maximize transient performance. The first order equation
(close approximation) for minimum inductance is:
where:
V
in
= Input Power Supply
V
out
= Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
V
ripple
= Maximum peak to peak output ripple voltage budget.
The first order equation for maximum allowed inductance is:
where:
C
o
= The total output capacitance
I
pp
= Maximum to minimum load transient current
V
tb
= The output voltage tolerance budget allocated to load
transient
D
m
= Maximum duty cycle for the DC/DC converter (usually
95%).
Some margin should be maintained away from both L
min
and
L
max
. Adding margin by increasing L almost always adds
expense since all the variables are predetermined by system
performance except for C
O
, which must be increased to
increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The RC5061 pro-
vides significant cost savings for the newer CPU systems
that typically run at high supply current.
RC5061 Short Circuit Current Characteristics
The RC5061 protects against output short circuit on the core
supply by turning off both the high-side and low-side
MOSFETs and resetting softstart. The short circuit limit is
set with the R
S
resistor, as given by the formula
with I
Detect
≈
50μA, I
SC
is the desired current limit, and
R
DS,on
the high-side MOSFET’s on resistance. Remember to
make the R
S
large enough to include the effects of initial tol-
erance and temperature variation on the MOSFET’s R
DS,on
.
Alternately, use of a sense resistor in series with the source
of the MOSFET eliminates this source of inaccuracy in the
current limit. The value of R
S
should be less than 8.3K
. If a
greater value is necessary, a lower R
DS,on
MOSFET should
be used instead.
As an example, Figure 4 shows the typical characteristic of
the DC-DC converter circuit with an FDB6030L high-side
MOSFET (R
DS
= 20m
maximum at 25°C * 1.25 at 75°C =
25m
) and a 8.2K
R
S
.
Figure 4. RC5061 Short Circuit Characteristic
The converter exhibits a normal load regulation characteristic
until the voltage across the MOSFET exceeds the internal
short circuit threshold of 50μA * 8.2K
= 410mV, which
occurs at 410mV/25m
= 16.4A. (Note that this current limit
level can be as high as 410mV/15m
= 27A, if the MOSFET
has typical R
DS,on
rather than maximum, and is at 25°C).
At this point, the internal comparator trips and signals the con-
troller to discharge the softstart capacitor. This causes a drastic
reduction in the output voltage as the load regulation collapses
into the short circuit control mode. With a 40m
output short,
L
min
(Vin
–
V
out
)
f
x
V
out
V
in
x
ESR
V
ripple
=
L
max
(Vin
–
V
out
) D
m
V
tb
I
pp2
= 2C
O
R
S
I
SC
*R
DS, on
I
Detect
=
V
O
(
0 5 10 15 20 25
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CPU Output Voltage vs. Output Current
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