
RC5060
PRODUCT SPECIFICATION
12
REV. 1.0.2 9/14/01
operation as a linear regulator. For this reason the RC5060
can provide up to 200mA of steady-state base current. The
TIP41A device shown has a sufficiently low V
CE, sat
to guaran-
tee worst-case regulation even at 2A I
E
with this base current.
RC5060 ACPI Control Lines
As already discussed, the RC5060 outputs are controlled by
the three ACPI control lines,
SLP_S3#
, SLP_S5# and
PWROK, as summarized in Tables 1 and 2. System design-
ers must in particular be careful to ensure that their system is
designed with SLP_S5#, not SLP_S5; if SLP_S5 is used, it
must be inverted before being used with the RC5060.
The control lines have internal pull-ups of approximately
10μA, and so can be controlled by open collector drivers if
desired. In a noisy system, it may be desirable to filter these
lines, which can be done with a 1K
resistor and a small
capacitor.
RC5060 Dynamic Operation
The RC5060 is designed to minimize the output capacitance
required to hold up the various output lines during transitions
between different states. Thus in particular, the 5V dual and
2.5V dual outputs have guaranteed minimum overlap times,
the time (as shown in Figure 2) during a state transition dur-
ing which both main and standby are connected to the out-
put. This overlap time guarantees that a power source is
always connected to the output, so that there will be no dip in
the output voltage during state transitions. There is also a
maximum overlap time, to ensure that the standby power
doesn’t have to source main power very long, thus minimiz-
ing thermal stress on the standby device.
The 3.3V dual and 3.3V SDRAM are different than the other
outputs, because they are powered by both a linear regulator
and a switch. If the linear regulator were to turn on while the
switch is on (or vice versa) the linear regulator would supply
power to the main line through the switch. For this reason,
the linear regulator must be off before the switch is on, and
vice versa. Thus, these two outputs have guaranteed minimum
deadtime when both linear regulator and switch are off. Dur-
ing this time, the output capacitors must hold up the load,
and so there is also a specified maximum deadtime, allowing
a maximum necessary capacitance to be selected, see below.
Stability
As with all linear regulators, the RC5060’s linear regulators
require a minimum load. With the exception of the 3.3V dual
output, however, all of these minimum loads are internal to
the RC5060. The 3.3V dual output requires a minimum load
of 50mA; if a situation may occur in which the load is less than
50mA, additional steps may be necessary to ensure stability.
Furthermore, depending on location, it may be necessary to
bypass the drain (or collector) of the linear regulator with a
low ESR capacitor for stability. As a rule of thumb, if the
pass element is more than 1” from its power source, it should
have a bypass.
Softstart
Pin 13 of the RC5060 functions as a softstart. When power is
first applied to the chip, a constant current is applied from
the pin into an external capacitor, linearly ramping up the
voltage. This ramp in turn controls the internal reference of
the RC5060. providing a softstart for the linear regulators.
The actual state of the RC5060 on power up will be deter-
mined by the state of its control lines.
The switches in the system must be either on or off, and so
softstart has no effect on their characteristics: if the appropri-
ate control signals are asserted, they will turn on at once.
The softstart is effective only during power on. During a
transition between states, such as from S5
→
S0, the linear
regulators are not softstarted.
It is important to note that the softstart pin is not an enable;
pulling it low will not necessarily turn off all outputs.
Charge Pump
In main power operation, the RC5060 is run from the +12V
main supply. This supply also provides voltage to the various
MOSFET gates. However, during standby, this supply is off.
To provide power to the chip and the appropriate gates, the
RC5060 incorporates a free-running charge pump. As shown
in Figures 4 and 5, and in the block diagram on the front
page, a capacitor attached between pins 1 and 2 of the RC5060
acts as a charge pump with internal diodes. The charge pump
output is internally diode or’red with the 12V input. The 12V
input must have a series diode to prevent back-feeding the
charge pump to the + 12V main when in standby. The 12V
input line needs a bypass capacitor for high-frequency noise
rejection.
Overcurrent
The RC5060 does not directly detect current through the
eight devices that power its outputs. Instead, it monitors the
four output voltages. In the event of a hard short, the voltage
drops below 80% of nominal, and all outputs are latched off,
and remain off until 5V standby power is recycled. The over-
current latch off is delayed by 150μsec to prevent nuisance trips.
In the S5 state, when the memory outputs are off, the voltage
monitors on the memory lines are disabled, to prevent trip-
ping the overcurrent. When turning these lines back on from
the S5 state, overcurrent is prevented from tripping because
the S3 state is blocked. See Table 2.
If the 2.5V dual is not used, its feedback line, pin 15, must be
connected to 5V dual as shown in Figure 5, to prevent an
overcurrent trip.
UVLO
If the +5V standby is below approximately 4.5V, the RC5060
will leave off or turn off all outputs. Similar comments apply
to the +12V main at 7.5V. The +5V standby UVLO has
approximately 0.5V hysteresis, the +12V main UVLO 1V.