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RC5054A
PRODUCT SPECIFICATION
10
MOSFET Selection/Considerations
The RC5054A requires 2 N-Channel power MOSFETs.
These should be selected based upon R
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipa-
tion, package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses
are the largest component of power dissipation for both the
upper and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor (see the
equations below). Only the upper MOSFET has switching
losses, since the Schottky rectifier clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not ade-
quately model power loss due the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the RC5054A and don't heat the MOSFETs.
However, large gate-charge increases the switching interval,
t
SW
, which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum junc-
tion temperature at high ambient temperature by calculating
the temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary depend-
ing upon MOSFET power, package type, ambient tempera-
ture and air flow.
Where: D is the duty cycle = V
OUT
/V
IN
,
t
SW
is the switching interval, and
F
S
is the switching frequency
Standard-gate MOSFETs are normally recommended for
use with the RC5054A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-
to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 7 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
CC
. The boot capacitor, C
BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V
D
) when the lower MOSFET,
Q2 turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V
CC
.
Figure 7. Upper Gate Drive - Bootstrap Option
Figure 8 shows the upper gate drive supplied by a direct con-
nection to V
CC
. This option should only be used in converter
systems where the main input voltage is +5V
DC
or less. The
peak upper gate-to-source voltage is approximately V
CC
less
the input supply. For +5V main power and +12VDC for the
bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage
rating exceeds the maximum voltage applied to V
CC
.
Figure 8. Upper Gate Drive - Direct V
CC
Drive Option
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.
P
UPPER
I
O
2
R
DS ON
)
D
1
V
IN
t
SW
F
S
×
×
×
+
×
×
=
P
LOWER
I
O
2
R
DS ON
)
1
D
–
(
)
×
×
=
+12V
+5V
PGND
RC5054A
GND
LGATE
UGATE
PHASE
BOOT
VCC
NOTE:
V
G-S
≈
V
CC
-V
D
NOTE:
V
G-S
≈
V
CC
C
BOOT
D
BOOT
Q1
Q2
+
-
D2
+12V
PGND
RC5054A
GND
LGATE
UGATE
PHASE
BOOT
V
CC
+5V OR LESS
NOTE:
V
G-S
≈
V
CC
-5V
NOTE:
V
G-S
≈
V
CC
Q1
Q2
+
-
D2