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RC6100
PRODUCT SPECIFICATION
6
Pin Descriptions
Pin Name
CVIN
FILTOUT
FILTIN
Pin Number
1
2
3
Description
This input accepts composite video.
Output of low pass video input filter.
This input accepts either composite video, composite sync or horizontal sync
signals. The input can be analog (1 Vpp) or TTL/CMOS logic levels.
Horizontal lock-detect timing capacitor.
+5V power supply for analog circuits.
This input accepts vertical sync pulses for use when video input signals do not
contain vertical sync components. This input is active low but remains high in
normal operation. The input is TTL or CMOS compatible.
The locked-loop output indicates that the oscillator is phase-locked to the incoming
horizontal sync. Sensitivity and delay time constant are set by an external
capacitor. This output is CMOS or TTL compatible.
Clamp gate pulse output. This signal is approximately 4
from the trailing edge of composite sync signal. The clamp gate is used by the
video ADC and other video processing circuitry for DC restoration. This output is
CMOS or TTL compatible.
+5V power supply for digital circuits.
Vertical sync signal output. This output is low during the line following the first
serration pulse in the vertical sync interval. VRESET is CMOS or TTL compatible.
CLKOUT divided-by-two output frequency.
The field ID output signal is low following the VRESET pulse of RS170 field 1. This
output is CMOS or TTL compatible.
Digital ground.
Horizontal reset signal is decoded from a programmable counter. This signal is
coherent with the clock output and is one clock cycle in duration. This output is
CMOS or TTL compatible.
Horizontal frequency signal input; normally driven by FHOUT.
Horizontal frequency signal output.
Frequency select inputs. They select one of four possible clock frequencies by
providing the appropriate divide-by-N for the frequency-multiplying PLL. Table 1
shows the binary, frequency select codes. These inputs are TTL or CMOS
compatible.
Clock input for internal timing functions; normally driven by CLKOUT.
Buffered VCO output signal.
This pin is used to select between NTSC or PAL frequencies of operation. A logic
one selects the NTSC frequencies. See Table 1. These inputs are TTL or CMOS
compatible.
Analog ground.
Composite sync signal output. This signal is the sync separated from the video
input, and is CMOS or TTL compatible.
PLL loop-compensation filter input.
HLCAP
V
CC
VSYNC
4
5
6
HLOCK
7
CLAMP
8
m
s in duration and is timed
V
VRESET
DD
9
10
CLKDIV2
FIELDID
11
12
V
HRESET
SS
13
14
FHIN
FHOUT
S0, S1
15
16
17, 18
CLKIN
CLKOUT
NTSC/PAL
19
20
21
GNDA
CSYNC
22
23
PLLFILTER
24