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RC5039
PRODUCT SPECIFICATION
10
P
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MVGX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The RC5039 requires an N-channel power MOSFET. It
should be selected based upon R
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipa-
tion, package selection and heatsink are the dominant design
factors. The power dissipation includes two loss compo-
nents; conduction loss and switching loss. The conduction
losses are the largest component of power dissipation for the
MOSFET. Switching losses also contribute to the overall
MOSFET power loss (see the equations below). These
equations assume linear voltage-current transitions and
are approximations. The gate-charge losses are dissipated by
the RC5039 and don't heat the MOSFET. However, large
gate-charge increases the switching interval, t
SW
, which
increases the upper MOSFET switching losses. Ensure that
the MOSFET is within its maximum junction temperature at
high ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications.
A separate heat-sink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
Where: D is the duty cycle = V
OUT
/V
IN
,
t
SW
is the switching interval, and
Fs is the switching frequency
Standard-gate MOSFETs are normally recommended for
use with the RC5039. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 8 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
CC
. The boot capacitor, C
BOOT
,
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V
D
) when the Schottky diode, D2,
conducts. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V
CC
.
Figure 8. Upper Gate Drive - Bootstrap Option
Figure 9 shows the upper gate drive supplied by a direct con-
nection to VCC . This option should only be used in con-
verter systems where the main input voltage is + 5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +
12VDC for the bias, the gate-to-source voltage of Q1 is 7V.
A logic-level MOSFET is a good choice for Q1 under these
conditions.
Figure 9. Upper Gate Drive - Direct V
CC
Drive Option
Schottky Selection
Rectifier D2 conducts when the upper MOSFET Q1 is off.
The diode should be a Schottky type for low power losses.
The power dissipation in the Schottky rectifier is approxi-
mated by:
Where: D is the duty cycle = V
O
/V
IN
, and
V
f
is the Schottky forward voltage drop
In addition to power dissipation, package selection and heat-
sink requirements are the main design tradeoffs in choosing
the Schottky rectifier. Since the three factors are interrelated,
P
COND
I
O
2
R
DS ON
)
D
′
′
=
P
SW
1
O
V
IN
t
SW
Fs
′
′
′
=
+12V
RC5039
GND
UGATE
PHASE
BOOT
VCC
+5V
NOTE:
V
G-S
V
CC
-V
D
C
BOOT
D
BOOT
Q1
D2
+
-
V
D
+
-
+12V
RC5039
GND
UGATE
PHASE
BOOT
VCC
+5V OR LESS
NOTE:
V
G-S
V
CC
-5V
Q1
D2
+
-
P
D
I
O
V
f
1
D
–
(
)
′
′
=