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PRODUCT SPECIFICATION
RC7104
13
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes when Spread Spectrum
is turned off
Data Byte 6
7
6
5
4
3
2
1
0
—
—
24
—
—
—
27
—
—
—
IOAPIC
—
—
—
REF
—
(Reserved)
(Reserved)
Clock Output disable
(Reserved)
(Reserved)
(Reserved)
Clock Output disable
(Reserved)
—
—
Low
—
—
—
Low
—
—
—
Active
—
—
—
Active
—
0
0
1
0
0
0
1
0
Input Conditions
Data Byte 3, Bit 3 = 1
Bit 5
SEL_1
0
0
1
1
0
0
1
1
Output Frequency
Bit 6
SEL_2
0
0
0
0
1
1
1
1
Bit 4
SEL_0
0
1
0
1
0
1
0
1
CPU, SDRAM
Clocks (MHz)
124.3
75.2
83.5
66.8
103.2
112.3
133.6
100.2
PCI Clocks
(MHz)
62.2
37.6
41.8
33.4
34.4
37.4
44.5
33.4
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes when Spread Spectrum
is turned on
Input Conditions
Data Byte 3, Bit 3 = 1
Bit 5
SEL_1
0
0
1
1
0
0
1
1
Output Frequency
Spread Percentage
±
0.25% Center
±
0.25% Center
±
0.25% Center
±
0.25% Center
±
0.25% Center
±
0.25% Center
±
0.25% Center
±
0.25% Center
CPU, SDRAM
Clocks (MHz)
124
75
83.3
66.8
103
112
133.3
100
Bit 6
SEL_2
0
0
0
0
1
1
1
1
Bit 4
SEL_0
0
1
0
1
0
1
0
1
PCI Clocks
(MHz)
41.3
37.5
41.6
33.4
34.25
33.3
44.43
33.3
Table 4. Data Bytes 3-6 Serial Configuration Map
(continued)
Bit(s)
Affected Pin
Pin No.
Bit Control
Pin Name
Control Function
0
1
Default