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RC7101
PRODUCT SPECIFICATION
6
A
RC7101 I
2
C Interface Write Sequence
Application Circuit
MSB
1
1
2
3
4
5
6
7
8
A
1
2
2
3
8
A
1
2
8
A
8
A
1
1
0
1
0
0
1
0
MSB
MSB
MSB
LSB
LSB
LSB
STOP
START
SDATA
SCLK
SDATA
(ACK Signal
From Buffer Chip)
LSB
RC7101 Slave Address (First Byte)
Signal from Motherboard Clock Chip
Command Code (2nd Byte)
Byte Count (3rd Byte)
Last Data Byte
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDATA at every 8th bit. The 8 bit data
from SDATA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected
The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
VDD
V
SS
22
R
S
*
0.1
μ
F
Cd*
2.2nF
*Each VDD pin should be separately decoupled with a 2.2nF capacitor.
SCLK
SDRAM (0:17)
SDATA
BUF_IN
CPUCLK
I
2
C
Control
RC7101
Clock
Generator
RC7101
3.3V Supply
L = 32
@ 100MHz
Recommended Isolation
100
μ
F
Multi-Via
Ground Connection
33
μ
F
OE
Output Enable
22
R
S