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RC7104
PRODUCT SPECIFICATION
8
A
48MHz and 24MHz Clock Output (Lump Capacitance Test Load = 20pF=66.6/100MHz)
CPU = 66.6MHz
Typ.
48.008
24.004
+167
57/17
Units
MHz
Parameter
f
Min.
Max.
Test Condition/Comments
Determined by PLL divider ratio
(see n/m below).
(48.008 – 48)/48
(14.31818MHz x 57/17 =
48.008MHz)
Measured from 0.4V to 2.4V.
Measured from 2.4V to 0.4V.
Measured on rising and falling
edge at 1.5V.
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
Assumes full supply voltage
reached within 1ms from power-up.
Frequency, Actual
f
D
n/m
Deviation from 48MHz
PLL Ratio
ppm
t
R
t
F
t
D
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45%
2
2
V/ns
V/ns
%
55
t
JC
Jitter, Cycle-to-Cycle
500
ps
f
ST
Frequency Stabilization
from Power-up
(cold start)
AC Output Impedance
3
ms
Z
0
20
ohm
Average value during switching
transition. Used for determining
series termination value.