I Balanced power/performance The fast speeds that SuperH devices provide would not be usable by portabl" />
參數(shù)資料
型號: R8J73437BGZV
廠商: Renesas Electronics America
文件頁數(shù): 3/46頁
文件大?。?/td> 0K
描述: SH-MOBILE 3AS
產(chǎn)品培訓(xùn)模塊: Electromagnetic Noise Reduction Techniques Part 1
標(biāo)準(zhǔn)包裝: 1
系列: SH-Mobile
核心處理器: SH-4A
芯體尺寸: 32-位
速度: 216MHz
連通性: I²C
外圍設(shè)備: DMA,LCD,WDT
輸入/輸出數(shù): 176
程序存儲器類型: ROMless
RAM 容量: 16M x 8
電壓 - 電源 (Vcc/Vdd): 1.1 V ~ 1.3 V
封裝/外殼: 模塊
包裝: 托盤
I Balanced power/performance
The fast speeds that SuperH devices provide would
not be usable by portable applications if the chips’
power dissipation was excessive. Therefore, Renesas
has designed the RISC and RISC/DSP devices in
low-power
sub-micron
CMOS
processes
with
low-voltage capabilities. Low static operating current
is achieved in all circuit designs; low dynamic (peak)
currents are guaranteed by logic and circuit design.
Power-reducing techniques used in cache design
– The sense amplifiers utilize SRAM circuit-design techniques
that reduce word-line voltage swings; this permits lower
currents to be used without sacrificing speed
– A unique cache-way-enable circuit minimizes power demands by
turning on the sense amplifiers only in that portion of the cache
that has a “hit” in a given access; this reduces the cache data
array's operating current by 75%
Software-controlled power-reduction mechanisms:
– Each device family offers a selection of power-reduction
techniques from a palette that includes Standby and Sleep
modes, clock-speed control and selective module shutdown
– Low operating and standby currents for longer battery life.
Hardware acceleration further reduces power consumption
– Video, imaging, graphics, and security engines significantly
improve computational speeds while minimizing power
consumption
I High integration
Renesas meets the dual needs for compact devices and
low system cost by providing a broad choice of on-chip
memories and peripherals in the SuperH series.
Large size and high performance on-chip memory: Up to
1MB on-chip flash memory, up to 128KB on-chip RAM,
and up to 32KB instruction and 32KB data cache
4- to 12-channel DMAC, 2 to 5 SCIs, 16-bit and
32-bit timers (3 to 34 channels), up to 149 I/O ports,
RTC, analog interfaces (4 to 32 channels), I2C,
CAN (up to 2 channels), others
All SuperH-series processors feature direct
interfaces to external memories. The on-chip Bus State
Controller, via the external bus, provides the specialized
inputs, outputs and functions for different types, widths,
and speeds of external memory (8/16/32-bit interfaces to
DRAM, SDRAM, DDR-SDRAM, flash, ROM, etc.)
I Best cost/performance
The SuperH architecture has a superior performance-
to-price ratio (Dhrystone MIPS/$). The architecture’s
16-bit RISC instruction set reduces system memory
requirements, which lowers the overall cost of
embedded system designs.
I Superior floating point and DSP support
The SuperH Family of processors with Floating Point Unit
(SH-2A, SH-4, SH-4A) and DSP (SH2-DSP, SH3-DSP,
SH-Mobile) support allow users to achieve more with
less, reducing overall system cost and power consumption
The SH-4 FPU is ideal for computer graphics and
can be utilized to efficiently implement multimedia
and networking operations
Top Reasons To Select SuperH
9
JPEG image compression/expansion
processing performance:
10 times higher than SH-1
3 times higher than SH-3
JPEG compression processing time
(in seconds)
0123
5
4
20MHz
SH-1
5.3
28MHz
SH-2
3.36
60MHz
SH-3
1.56
60MHz
SH2-DSP
0.55
Image size (VGA): 640x480
24-bit full color
Y: Cr: Cb = 4: 2: 2
Compression ratio: 1/10
SH2-DSP Signal Processing Performance
TOP REASONS TO SELECT SuperH
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