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32142D–06/2013
ATUC64/128/256L3/4U
5.
Memories
5.1
Embedded Memories
Internal high-speed flash
– 256Kbytes (ATUC256L3U, ATUC256L4U)
– 128Kbytes (ATUC128L3U, ATUC128L4U)
– 64Kbytes (ATUC64L3U, ATUC64L4U)
0 wait state access at up to 25MHz in worst case conditions
1 wait state access at up to 50MHz in worst case conditions
Pipelined flash architecture, allowing burst reads from sequential flash locations, hiding
penalty of 1 wait state access
Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation
to only 8% compared to 0 wait state operation
100 000 write cycles, 15-year data retention capability
Sector lock capabilities, bootloader protection, security bit
32 fuses, erased during chip erase
User page for data to be preserved during chip erase
Internal high-speed SRAM, single-cycle access at full speed
– 32Kbytes (ATUC256L3U, ATUC256L4U, ATUC128L3U, ATUC128L4U)
– 16Kbytes (ATUC64L3U, ATUC64L4U)
5.2
Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even during boot. Note that AVR32 UC CPU uses unseg-
mented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address
space is mapped as follows:
Table 5-1.
ATUC64/128/256L3/4U Physical Memory Map
Memory
Start Address
Size
ATUC256L3U, ATUC256L4U
ATUC128L3U, ATUC128L4U
ATUC64L3U, ATUC64L4U
Embedded SRAM
0x00000000
32Kbytes
16Kbytes
Embedded Flash
0x80000000
256Kbytes
128Kbytes
64Kbytes
SAU Channels
0x90000000
256 bytes
HSB-PB Bridge B
0xFFFE0000
64Kbytes
HSB-PB Bridge A
0xFFFF0000
64Kbytes
Table 5-2.
Flash Memory Parameters
Device
Flash Size (FLASH_PW)
Number of Pages (FLASH_P)Page Size (FLASH_W)
ATUC256L3U,
ATUC256L4U
256Kbytes
512
512 bytes
ATUC128L3U,
ATUC128L4U
128Kbytes
256
512 bytes
ATUC64L3U,
ATUC64L4U
64Kbytes
128
512 bytes