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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | R5F5630ADDFB#V0 |
| 寤犲晢锛� | Renesas Electronics America |
| 鏂囦欢闋佹暩(sh霉)锛� | 63/165闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU RX630 768KB FLASH 144-LQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | RX Compare Match Timer RX DMAC |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | RX600 |
| 鏍稿績铏曠悊鍣細 | RX |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 100MHz |
| 閫ｉ€氭€э細 | CAN锛孍BI/EMI锛孖²C锛孡IN锛孲CI锛孲PI锛孶SB |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孡VD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 117 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 768KB锛�768K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 96K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b锛�21x12b锛孌/A 2x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 144-LQFP |
| 鍖呰锛� | 鎵樼洡 |
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R01DS0060EJ0100 Rev.1.00
Page 155 of 168
Sep 13, 2011
RX630 Group
5. Electrical Characteristics
5.13
E2 Flash Characteristics
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 128-byte programming is performed 16 times for different
addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (over writing is prohibited).
Note 2. This indicates the minimum number that guarantees the characteristics after reprogramming. (The guaranteed value is in the
range from one to the minimum number.)
Note 3. This indicates the characteristic when reprogram is performed within the specification range including the minimum number.
Table 5.30
E2 Flash Characteristics
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = Topr
Item
Symbol
FCLK = 4 MHz
20 MHz
鈮� FCLK 鈮� 50 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Programming time
NPEC 100 hours
2 bytes
tDP2
鈥�
0.7
6
鈥�
0.25
2
ms
Programming time
NPEC > 100 hours
2 bytes
tDP2
鈥�
0.7
6
鈥�
0.25
2
ms
Erasure time
NPEC 100 hours
32 bytes
tDE32
鈥�4
40
鈥�2
20
ms
Erasure time
NPEC > 100 hours
32 bytes
tDE32
鈥�7
40
鈥�4
20
ms
Blank check time
2 bytes
tDBC2
鈥�
100
鈥�
30
渭s
Reprogram/erase cycle*1
NDPEC
100000*2
鈥�
100000*2
鈥斺€�
Times
Suspend delay time during programming
tDSPD
鈥�
250
鈥�
120
渭s
First suspend delay time during erasing
(in suspend priority mode)
tDSESD1
鈥�
250
鈥�
120
渭s
Second suspend delay time during erasing
(in suspend priority mode)
tDSESD2
鈥�
500
鈥�
300
渭s
Suspend delay time during erasing
(in erasure priority mode)
tDSEED
鈥�
500
鈥�
300
渭s
Data hold time*3
tDDRP
10
鈥�
10
鈥�
Year
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| R5F5630ADDLC | 鍒堕€犲晢:RENESAS 鍒堕€犲晢鍏ㄧū:Renesas Technology Corp 鍔熻兘鎻忚堪:Renesas MCUs |
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