參數(shù)資料
型號： R5F562N8BDBG#U0
廠商： Renesas Electronics America
文件頁數(shù)： 93/148頁
文件大小： 0K
描述： MCU 32BIT FLASH 512K ROM 176BGA
產(chǎn)品培訓模塊： RX USB Peripheral
CAN Peripheral and API
RX 12-Bit ADC
RX Bus State Controller
RX Low Voltage Detection and Reset Sources
RX Watchdog Timer
RX 10-Bit ADC
RX 10-Bit DAC
RX Core
RX Compare Match Timer
RX DMAC
特色產(chǎn)品： RX600 Series Microcontrollers
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 126
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LFBGA
包裝： 托盤
2004 Microchip Technology Inc.
DS39609B-page 47
PIC18F6520/8520/6620/8620/6720/8720
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. The data
memory map is in turn divided into 16 banks of
256 bytes each. The lower 4 bits of the Bank Select
Register (BSR<3:0>) select which bank will be
accessed. The upper 4 bits of the BSR are not
implemented.
The data memory space contains both Special Func-
tion Registers (SFR) and General Purpose Registers
(GPR). The SFRs are used for control and status of the
controller and peripheral functions, while GPRs are
used for data storage and scratch pad operations in the
user’s application. The SFRs start at the last location of
Bank 15 (0FFFh) and extend downwards. Any remain-
ing space beyond the SFRs in the Bank may be imple-
mented as GPRs. GPRs start at the first location of
Bank
0
and
grow
upwards.
Any
read
of
an
unimplemented location will read as ‘0’s.
PIC18FX520 devices have 2048 bytes of data RAM,
extending from Bank 0 to Bank 7 (000h through 7FFh).
PIC18FX620
and
PIC18FX720
devices
have
3840 bytes of data RAM, extending from Bank 0 to
Bank 14 (000h through EFFh). The organization of the
data memory space for these devices is shown in
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFF instruction. The
MOVFF
instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
“Access Bank” provides a detailed description of the
Access RAM.
4.9.1
GENERAL PURPOSE
REGISTER FILE
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation
of
indirect
addressing
is
shown
in
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as General Purpose
Registers by all instructions. The top section of Bank 15
(F60h to FFFh) contains SFRs. All other banks of data
memory contain GPR registers, starting with Bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-2 and Table 4-3.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature. The
SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations are unimplemented and
read as ‘0’s. The addresses for the SFRs are listed in
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F562N8BDFB 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 144QFP
R5F562N8BDFB#V0 功能描述:MCU 32BIT FLASH 512K ROM 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:RX600 標準包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲器容量:8KB（8K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285
R5F562N8BDFP 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 100QFP
R5F562N8BDFP#V0 功能描述:MCU 32BIT FLASH 512K ROM 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:RX600 標準包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲器容量:8KB（8K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285
R5F562N8BDLE 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 145LGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 145LGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 145LGA; Controller Family/Series:RX600; Core Size:32bit; No. of I/O's:103; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Digital IC Case Style:LGA; No. of Pins:145; Program Memory Size:512KB; RAM Memory ;RoHS Compliant: Yes
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