參數(shù)資料
型號： R5F562N8ADBG#U0
廠商： Renesas Electronics America
文件頁數(shù)： 32/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512KROM 176LFBGA
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 126
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LFBGA
包裝： 托盤
2004 Microchip Technology Inc.
DS39609B-page 125
PIC18F6520/8520/6620/8620/6720/8720
10.9
PORTJ, TRISJ and LATJ
Registers
PORTJ is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
PORTJ is multiplexed with the system bus as the exter-
nal memory interface; I/O port functions are only avail-
able when the system bus is disabled. When operating
as the external memory interface, PORTJ provides the
control signal to external memory devices. The RJ5 pin
is not multiplexed with any system bus functions.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTJ pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-9:
INITIALIZING PORTJ
FIGURE 10-20:
PORTJ BLOCK DIAGRAM
IN I/O MODE
Note:
PORTJ is available only on PIC18F8X20
devices.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
CLRF
PORTJ
; Initialize PORTG by
; clearing output
; data latches
CLRF
LATJ
; Alternate method
; to clear output
; data latches
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISJ
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
Data
Bus
WR LATJ
WR TRISJ
RD PORTJ
Data Latch
TRIS Latch
RD TRISJ
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LATJ
or
PORTJ
Note 1: I/O pins have diode protection to VDD and VSS.
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