參數(shù)資料
型號(hào): R5F562N7ADFB#V0
廠商: Renesas Electronics America
文件頁(yè)數(shù): 75/148頁(yè)
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 384KROM 144LQFP
產(chǎn)品培訓(xùn)模塊: RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SCI,SPI,USB
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 103
程序存儲(chǔ)器容量: 384KB(384K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10/12b,D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤(pán)
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)當(dāng)前第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 30
2004 Microchip Technology Inc.
3.1
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, tie the MCLR pin through a 1 k
to 10 k
resistor to VDD. This will eliminate external RC
components usually needed to create a Power-on
Reset delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.3
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to
provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
3.5
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. If the Power-up Timer is enabled, it will be
invoked after VDD rises above BVDD; it then will keep
the chip in Reset for an additional time delay (parame-
ter #33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figures 3-3 through 3-7 depict time-out sequences on
power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 k
is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 = 1 k
to 10 k will limit any current flow-
ing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC18FXX20
相關(guān)PDF資料
PDF描述
D38999/26MD19SA CONN PLUG 19POS STRAIGHT W/SCKT
MS27467E25F35SC CONN PLUG 128POS STRAIGHT W/SCKT
VI-B6V-IW-F1 CONVERTER MOD DC/DC 5.8V 100W
031-4890-1 CONN RCPT BNC ISOLATED BLKHD
VI-BV4-IX-F4 CONVERTER MOD DC/DC 48V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F562N7ADFP 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 100QFP 制造商:Renesas Electronics Corporation 功能描述:MCU32Bit 165MIPS ROM384KRAM32K QFP100Pin
R5F562N7ADFP#V0 功能描述:MCU 32BIT FLASH 384KROM 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:RX600 標(biāo)準(zhǔn)包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C,SPI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位,POR,PWM,WDT 輸入/輸出數(shù):11 程序存儲(chǔ)器容量:3.5KB(2K x 14) 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP(0.173",4.40mm 寬) 包裝:管件
R5F562N7ADLE 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 145LGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 145LGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 145LGA; Controller Family/Series:RX600; Core Size:32bit; No. of I/O's:103; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Digital IC Case Style:LGA; No. of Pins:145; Program Memory Size:384KB; RAM Memory ;RoHS Compliant: Yes
R5F562N7ADLE#U0 功能描述:MCU 32BIT FLASH 384KROM 145TFLGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:RX600 標(biāo)準(zhǔn)包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C,SPI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位,POR,PWM,WDT 輸入/輸出數(shù):11 程序存儲(chǔ)器容量:3.5KB(2K x 14) 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP(0.173",4.40mm 寬) 包裝:管件
R5F562N7BDBG 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 176BGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 176BGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 176BGA; Controller Family/Series:RX600; Core Size:32bit; No. of I/O's:126; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Digital IC Case Style:LFBGA; No. of Pins:176; Program Memory Size:384KB; RAM Memory ;RoHS Compliant: Yes