參數(shù)資料
型號: R5F56217BDLD#U0
廠商: Renesas Electronics America
文件頁數(shù): 6/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 384KROM 85TFLGA
產(chǎn)品培訓模塊: RX Compare Match Timer
RX DMAC
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,SCI,SPI,USB
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 58
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10/12b,D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 85-TFLGA
包裝: 托盤
2004 Microchip Technology Inc.
DS39609B-page 101
PIC18F6520/8520/6620/8620/6720/8720
9.5
RCON Register
The RCON register contains the IPEN bit, which is
used to enable prioritized interrupts. The functions of
the other bits in this register are discussed in more
REGISTER 9-13:
RCON REGISTER
R/W-0
U-0
R/W-1
R-1
R/W-0
IPEN
—RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1
= Enable priority levels on interrupts
0
= Disable priority levels on interrupts (PIC16 Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-4.
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-4.
bit 2
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-4.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-4.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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