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參數(shù)資料
| 型號(hào)： | R5310L |
| 廠商： | Ricoh Co., Ltd. |
| 英文描述： | Multi LDOs for Cellular-phone |
| 中文描述： | 低壓降穩(wěn)壓器多為蜂窩電話 |
| 文件頁數(shù)： | 17/34頁 |
| 文件大小： | 270K |
| 代理商： | R5310L |
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Rev.1.10
- 17 -
I
TECHNICAL NOTES
G
Operation with rising and falling of Supply Voltage
1.
Supply voltage condition --- from 0V to a designated voltage
To make the explanation be easier, we call a voltage which is monitored and rising voltage threshold, as “Released Voltage”.
On the contrary, we call the falling voltage threshold as “Detector Threshold Voltage”. And the difference between them is
specified as a Hysteresis Voltage.
While the supply voltage is from 0V to VD2 (Released Voltage), all the circuits except VDs are “OFF” state, thus both
levels of D
OUT1
and
2
are “L”. However, we cannot guarantee the operation with a V
DD
at voltage below the minimum
operating voltage (V
DDMIN
) with both a rising and a falling conditions. When the supply voltage crosses over the Released
Voltage for VD2, D
OUT2
becomes “H” and VR6 is enabled.
Further, when R
OUT6
crosses over the Released Voltage for VD1, after a setting delay time by an external capacitor to C
D
pin,
D
OUT1
becomes “H”, then internal logic circuits and reset condition for input control pins (3-wire interface inputs and CSWx
etc.) are released. Therefore circuits' operations can become to control by these input pins.
2.
Supply voltage condition --- from a designated voltage to 0V
When the supply voltage becomes lower than Detector Threshold Voltage for VD2, D
OUT2
becomes “L” and disables VR6.
Further, VR6 level becomes lower than Detector Threshold Voltage for VD1, then D
OUT1
becomes “L” and reset internal
logic circuits and input controller pins (3-wire inputs and CSWx etc.)
Then all the circuits except VDs are OFF (See the Note below), and input signals for control are not accepted.
The lower voltage than this is as same as above.
<Note>
As for VR1, when supply voltage is equal or less than Detector Threshold Voltage for VD2, output is indefinite
(ON/OFF). At this condition, both CSW1 pin input and 3-wire controller inputs cannot be accepted.
This operation could cause a problem on your system, and should be considered enough.
G
Block Diagram of VDs
VD1
(for Reset CPU)
V
DET
=2.7V
VD2
(detect battery
out off)
V
DET
=3V
VD3
(protection for
over input voltage)
V
DET
=6.3V
VD4
(protection
for coin battery)
V
DET
=3.45V
V
DD
IBC6
R
OUT6
D
OUT2
C
D
D
OUT1
LN
CSW
IBC6
OUT
VR6
Logic Circuits
Reset
FN
Gate Circuits
Digital Inputs
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