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Rev. 1.12 - 8 -
I
Timing Chart
V
IN
Voltage
V
UVLO2
V
OUT1
Voltage
Soft-start Time
VDDelay for Release
V
DOUT
Voltage
V
UVLO1
-
Vdet
(-Vdet+Vhys)
VD
Delay for
Release
Lx
Voltage
V
OUT2
Voltage
The timing chart which is shown in the previous page describes the relation of supply voltage changes with
time and each output of DC/DC converter, voltage detector, and voltage regulator.
(1) DC/DC converter
When the power turns on and in the case of rising the V
IN
voltage, while the V
IN
voltage is at UVLO release
level (V
UVLO2
) or less, the operation of the DC/DC converter stops and does not make switching, therefore
V
OUT1
voltage does not rise.
When the V
IN
voltage becomes UVLO release level or more, the DC/DC converter starts soft-start
operation, and start switching, then V
OUT1
will rise. After the soft-start time, if V
IN
voltage becomes set
V
OUT1
level or more, V
OUT1
will be settled at V
OUT1
set output voltage. If V
IN
voltage becomes UVLO
detector threshold level (V
UVLO1
) or less, the DC/DC converter stops switching then Lx transistor in the IC
turns off.
(2) Voltage Detector
If the V
IN
voltage is at VD detector threshold level or less, the N-channel transistor of V
DOUT
pin turns on
and outputs “L” to V
DOUT
pin. Then, when the V
IN
voltage becomes VD detector threshold level + its
hysteresis range (-V
DET
+V
HYS
) or more, after VD delay for release (tpLH) passing, the N-channel transistor
inside the IC turns off, V
DOUT
pin voltage reaches to the pull-up voltage. Besides, the release circuit for VD
starts after soft-start time and under this condition, V
IN
voltage should be (-V
DET
+V
HYS
) or more.
(3) Voltage Regulator
The voltage regulator always operates even if UVLO function would work. Therefore, V
OUT2
voltage is
nearly equal to V
IN
voltage. Actual value depends on the load current. When the V
IN
voltage becomes set
V
OUT2
voltage or more, V
OUT2
voltage will be the set output voltage.
I
TEST CIRCUITS
A) Supply Current
B) UVLO Detector Threshold/ Released Voltage