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參數(shù)資料
| 型號： | R5109G511C-TR-FE |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, SSOP-8 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 275K |
| 代理商： | R5109G511C-TR-FE |
R5109G
10
If the almost same timing input of SCK1 and SCK2 continues twice, the WDT will be cleared. (as the status
(13))
t
SCK2
SCK1
0~50ns
Example timing of too close input pulses
(This pattern will be recognized the clock timing is same by the WDT)
Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s)
= 3.1 × 106 × C (F)
tWR (s)
= tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s)
= tWD/10
Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation
describes the relation between the capacitance value and the released delay time (tPLH).
tPLH (s)
=3.7 × 106 × C (F)
The capacitor connected to CD pin determines tWD, tWR, and tPLH.
When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin
starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay
time will be shorter than tPLH which is expected.
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