參數(shù)資料
型號(hào): R2051K
英文描述: real-time clock ICs
中文描述: 實(shí)時(shí)時(shí)鐘IC
文件頁數(shù): 12/53頁
文件大?。?/td> 343K
代理商: R2051K
R2051 Series
I
Address Mapping
Address
A3A2A1A0
0 0 0 0 0
12345
Rev.1.04 - 12 -
Register Name
Second Counter
D a t a
D7
D6
-
*2)
-
M40
-
-
D5
S20
D4
S10
D3
S8
D2
S4
D1
S2
D0
S1
S40
1 0 0 0 1
2 0 0 1 0
Minute Counter
Hour Counter
M20
H20
P
/A
-
D20
-
M10
H10
M8
H8
M4
H4
M2
H2
M1
H1
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
Day-of-week Counter
Day-of-month Counter
Month Counter and
Century Bit
Year Counter
Oscillation Adjustment
Register *3)
Alarm_W
(Minute Register)
Alarm_W
(Hour Register)
Alarm_W
(Day-of-week Register)
Alarm_D
(Minute Register)
Alarm_D
(Hour Register)
Control Register 1 *3)
-
-
/19
20
-
-
-
-
D10
MO10
-
D8
MO8
W4
D4
MO4
W2
D2
MO2
W1
D1
MO1
6 0 1 1 0
7 0 1 1 1
Y80
DEV
*4)
-
Y40
F6
Y20
F5
Y10
F4
Y8
F3
Y4
F2
Y2
F1
Y1
F0
8 1 0 0 0
WM40 WM20 WM10
WM8
WM4
WH
4
WM2
WM1
9 1 0 0 1
-
-
WH20
WP
/ A
WW5
WH10
WH8
WH2
WH
1
WW0
A 1 0 1 0
-
WW6
WW4
WW3 WW2 WW1
B 1 0 1 1
-
DM40
DM20
DM10
DM8
DM4
DM2
DM1
C 1 1 0 0
-
-
DH20
DP
/A
-
/12
24
DH10
DH8
DH4
DH2
DH1
D 1 1 0 1
E 1 1 1 0
-
-
DALE
-
SCRA
TCH2
PON
*5)
-
TEST
-
CT2
-
CT1
-
CT0
WALE
F 1 1 1 1
Control Register 2 *3)
VDSL
VDET
/XST
SCRA
TCH1
CTFG WAFG
DAFG
Notes:
* 1) All the data listed above accept both reading and writing.
* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.
* 3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment
Register, Control Register 1 and Control Register 2 excluding the /XST bit.
* 4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or
loss up to
±
1.5ppm.
When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or
loss up to or
±
0.5ppm.
* 5) PON is a power-on-reset flag.
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