參數(shù)資料
型號: R2033T
廠商: Ricoh Co., Ltd.
英文描述: 3 wire interface Real-Time Clock ICs
中文描述: 3線接口實時時鐘芯片
文件頁數(shù): 40/50頁
文件大?。?/td> 542K
代理商: R2033T
R2033K/T
Periodic Interrupt
40
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform
modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%.
In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to
High (OFF).
CT2
CT1
CT0
Wave form
mode
0
0
0
-
OFF(H)
0
0
1
-
Fixed at “L”
0
1
0
Pulse Mode *1)
2Hz(Duty50%)
0
1
1
Pulse Mode *1)
1Hz(Duty50%)
1
0
0
Level Mode *2)
Once per 1 second (Synchronized with
Second counter increment)
1
0
1
Level Mode *2)
Once per 1 minute (at 00 seconds of every
Minute)
1
1
0
Level Mode *2)
Once per hour (at 00 minutes and 00
Seconds of every hour)
1
1
1
Level Mode *2)
Once per month (at 00 hours, 00 minutes,
and 00 seconds of first day of every month)
*1) Pulse Mode:
2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as
illustrated in the timing chart below.
Description
Interrupt Cycle and Falling Timing
(Default)
INTR Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
μ
s
(Increment of second counter)
In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the falling
edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may
appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the
second counter will reset the other time counters of less than 1 second, driving the INTR pin low.
*2) Level Mode:
Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour,
and 1 month. The increment of the second counter is synchronized with the falling edge of periodic
interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are
output in synchronization with the increment of the second counter as illustrated in the timing chart below.
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