
R2033K/T
19
digits in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to
12 and are carried to the year digits in reversion from 12 to 1.
The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08,
…
, 92, and 96 in leap years) and are carried to
the 19 /20 digits in reversion from 99 to 00.
The 19 /20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.
* Any carry from lower digits with the writing of non-existent calendar data may cause the calendar
counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent
calendar data.
Oscillation Adjustment Register (Address 7h)
D7
D6
D5
D4
D3
DEV
F6
F5
F4
F3
DEV
F6
F5
F4
F3
0
0
0
0
0
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
DEV bit
When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds.
When DEV is set to 1, the Oscillation Adjustment Circuit operates 00 seconds.
F6 to F0 bits
The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of
the settings of the Oscillation Adjustment Register at the timing set by DEV.
* The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds)
as the timing of writing to the Oscillation Adjustment Register.
* The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2.
The F6 bit setting of 1 causes a decrement of time counts by (( F
5
,F
4
,F
3
,F
2
,F
1
,F
0
) + 1) x 2.
The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and
F0 bits cause neither an increment nor decrement of time counts.
Example:
If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20, or
40, an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss).
If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20, 40,
neither an increment nor a decrement of the current time counts of 32768.
If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a
decrement of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain).
An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 /
(32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a
time count gain of 3 ppm. Consequently, when DEV is set to “0”, deviations in time counts can be
corrected with a precision of
±
1.5 ppm. In the same way, when DEV is set to “1”, deviations in time
counts can be corrected with a precision of
±
0.5 ppm. Note that the oscillation adjustment circuit is
configured to correct deviations in time counts and not the oscillation frequency of the 32.768-kHz clock
pulses. For further details, see "P32
Configuration of Oscillation Circuit and Correction of Time
Count Deviations
Oscillation Adjustment Circuit
".
D2
F2
F2
0
D1
F1
F1
0
D0
F0
F0
0
(For Writing)
(For Reading)
Default Settings *)