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參數(shù)資料
| 型號(hào)： | QT60248-ASG |
| 廠商： | Atmel |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SENSOR QMATRIX 24CHAN 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | QMatrix™, QProx™ |
| 類型： | 電容性 |
| 輸入數(shù)/鍵： | 24 鍵 |
| 分辨率（位）： | 9，11 b |
| 評(píng)估套件： | 可供 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 電源電壓： | 3 V ~ 5 V |
| 電流 - 電源： | 25mA |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 2822 (CN2011-ZH PDF) |
| 配用： | 427-1087-ND - BOARD EVAL QT60248-AS QMATRIX |
| 其它名稱： | 427-1108 |
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(DI) pin of the host. MISO floats when /SS is high to allow
multi-drop communications along with other slave parts.
SCK - SPI clock - input only clock from host. The host must
shift out data on the falling SCK edge; the QT60xx8 clocks
data in on the rising edge. The QT60xx8 likewise shifts data
out on the falling edge of SCK back to the host so that the
host can shift the data in on the rising edge. Important:
SCK must idle high; it should never float.
/SS - Slave select - input only; acts as a framing signal to the
sensor from the host. /SS must be low before and during
reception of data from the host. It must not go high again
until the SCK line has returned high; /SS must idle high.
This pin includes an internal pull-up resistor of 20K ~ 50K.
When /SS is high, MISO floats.
DRDY - Data Ready - active-high - indicates to the host that
the QT is ready to send or receive data. This pin idles high.
This pin includes an internal pull-up resistor of 20K ~ 50K.
In SPI mode this pin is an output only (i.e. open drain with
internal pull-up).
The MISO pin on the QT floats in 3-state mode between bytes
when /SS is high. This facilitates multiple devices on one SPI
bus.
Null Bytes: When the QT responds to a command with one or
more response bytes, the host should issue a null commands
(0x00) to get the response bytes back. The host should not
send new commands until all the responses are accepted back
from the QT from the prior command via nulls.
New commands attempted during intermediate byte transfers
are ignored.
SPI Line Noise: In some designs it is necessary to run SPI
lines over ribbon cable across a lengthy distance on a PCB.
This can introduce ringing, ground bounce, and other noise
problems which can introduce false SPI clocking or false data.
Simple RC networks and slower data rates as shown in Figure
3-2 are helpful to resolve these issues.
CRC checks have been added to critical commands in order to
detect transmission errors to a high level of certainty.
3.3 Command Error Handling
If an unrecognized command is received, the device will release
DRDY high and the communications error flag will be set in the
General Status byte (see Section 4.5).
4 Control Commands
Refer to Table 4.2, page 16 for further details.
The devices feature a set of commands which are used for
control and status reporting. The host device has to send the
command to the QT60xx8 and await a response.
SPI mode: While waiting the host should delay for 40s from
the end of the command, then start to check if DRDY is or goes
high. If it is high, then the host master can clock out the
resulting byte(s).
Command timeouts: Where a command involves multi-byte
transfers in either direction, each byte must be transmitted
within 100ms of the prior byte or the command will timeout. No
error is reported for this condition; the command simply ceases.
Word return byte order: Where a word or long word is
returned (16 or 24 bit number or bit pattern) the low order byte
is sent or received first.
4.1 Null Command - 0x00
Used to shift back data from the QT. Since the host device is
always the master in SPI mode, and data is clocked in both
directions, the Null command is required frequently to act as a
placeholder where the desire is to only get data back from the
QT, not to send a command.
In SPI communications, when the QT60xx8 responds to a
command with one or more response bytes, the host can issue
a new command instead of a null on the last byte shift
operation.
New commands during intermediate byte shift-out operations
are ignored, and null bytes should always be used.
lQ
11
QT60248-AS R4.02/0405
Figure 3-3 SPI Slave-Only Mode Timing
S1: m333ns
S2: [20ns
S3: m25ns
S4: [20ns
S5: [40s
S6: m1s
S7: m333ns
S8: m333ns
S9: m667ns
S6
high via pullup-R
DRDY
(from QT)
S1
S5
/SS
(from Host)
S3
CLK
(from Host)
MOSI
(Data from Host)
MISO
3-state
(Data from QT)
0
2
3
6
71
210
4
5
4
50
1
2
3
765
6
7
210
?
43
543
?
07
6
?
7654321
76543210
S7
S9
S8
Data shifts out of QT on falling edge
data response
{optional 2nd command byte}
{null byte or next command to get QT response}
Data shifts in to QT on rising edge
{Command byte}
S4
S2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QT60248-ASG SL683 | 制造商:Atmel Corporation 功能描述:Q Matrix IC 32-Pin TQFP |
| QT60248-ASG-SL683 | 功能描述:接口 - 專用 Integrated Circuit RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QT60248C-ASG | 功能描述:接口 - 專用 Integrated Circuit RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QT60248C-ASG-SL683 | 功能描述:接口 - 專用 Integrated Circuit RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QT60320 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32 KEY QMATRIX CHARGE TRANSFER IC |
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