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參數(shù)資料
| 型號(hào)： | QS5931-50Q |
| 英文描述： | Six Distributed-Output Clock Driver |
| 中文描述： | 六分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | QS5931-50Q |
3
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
t
R,
t
F
F
I
t
PWC
D
H
Parameter
(1)
Mn.
—
—
Typ.
—
—
—
—
—
—
—
Max.
500
500
Unit
ps
ps
ns
ns
ps
ms
ns
Output Skew Between Rising Edges, Q
0
-Q
4
(2,3)
Output Skew Between Falling Edges, Q
0
-Q
4
(2,3)
Pulse Width, Q
0
-Q
4
Cycle-to-Cycle Jitter
(2,5)
CLK_IN to Feedback Delay
(2,6)
CLK_IN to Phase Lock
Output Enable Time, OE/
RST
LOW to HIGH
(4)
T
CYC
/2
0.4
0.15
500
—
0
T
CYC
/2 + 0.4
+0.15
+500
10
14
Output Disable Time, OE/
RST
HIGH to LOW
(2,4)
0
—
14
ns
Output Rise/Fall Times, 0.2V
DD
～
0.8V
DD
(2)
MaximumRise/Fall Times, 0.8V to 2V
Input Clock Frequency
Input Clock Pulse, HIGH or LOW
(7)
Duty Cycle, CLK_IN
(7)
—
—
10
2
25
—
—
—
—
—
2.5
3
80
—
75
ns
ns
MHz
ns
%
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. This parameter is guaranteed by characterization but not tested.
3. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
4. Measured in open loop mode PLL_EN = 0.
5. Jitter is characterized using an oscilloscope, Q output at 20MHz. Measurement is taken one cycle after jitter.
6. t
PD
measured at device inputs at 1.5V, Q output at 80MHz.
7. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, AV
DD/
V
DD
= 5.0V ± 10%
Symbol
V
IH
V
IL
V
OH
Parameter
Conditions
Mn.
2
—
Typ.
—
—
—
—
—
—
100
—
Max.
—
0.8
—
—
0.45
0.2
—
±5
Unit
V
V
V
V
V
V
mV
μ
A
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
I
OH
=
36mA
I
OH
=
100
μ
A
V
DD
= Mn., I
OL
= 36mA
V
DD
= Mn., I
OL
= 100
μ
A
V
DD
– 0.75
V
DD
– 0.2
—
—
—
—
V
OL
Output LOW Voltage
V
H
I
OZ
Input Hysteresis
Output Leakage Current
—
V
OUT
= V
DD
or GND,
V
DD
= Max., Outputs Disabled
V
IN
= AV
DD
or GND, AV
DD
= Max.
I
IN
Input Leakage Current
—
—
±5
μ
A
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
Parameter
Test Conditions
Typ.
—
Max.
1
Unit
mA
Quiescent Power Supply Current
V
DD
= Max., OE/
RST
= LOW,
CLK_IN = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3.4V
V
DD
= Max., C
L
= 0pF
I
DD
I
DDD
Power Supply Current per Input HIGH
Dynamc Power Supply Current
(1)
0.7
—
1.5
0.4
mA
mA/MHz
NOTE:
1. This value is guaranteed but not tested.
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| QS5931-80Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Six Distributed-Output Clock Driver |
| QS5931Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SIX DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SSOP|20PIN|PLASTIC |
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