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參數(shù)資料
| 型號： | QLX4600SIQSR |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER REC 6.25GBPS 46QFN |
| 標準包裝： | 100 |
| 系列： | QLx™ |
| 應(yīng)用： | 銅電纜模塊 |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
15
FN6979.1
November 19, 2009
Control Pin Boost Setting
When register 1 of the QLx4600-S30 is zero (the default
state on power-up), the voltages at the CP pins are used
to determine the boost level of each channel. For each of
the four channels, k, the [A], [B], and [C] control pins
(CP[k]) are associated with a 3-bit non binary word.
While [A] can take one of two values, ‘LOW’ or ‘HIGH’,
[B] and [C] can take one of three different values: ‘LOW’,
‘MIDDLE’, or ‘HIGH’. This is achieved by changing the
value of a resistor connected between VDD and the CP
pin, which is internally pulled low with a 25kΩ resistor.
Thus, a ‘HIGH’ state is achieved by using a 0Ω resistor,
‘MIDDLE’ is achieved with a 25kΩ resistor, and ‘LOW’ is
achieved with an open resistance. Table 2 defines the
mapping from the 3-bit CP word to the 18 out of 32
possible levels available via the serial interface.
If all four channels are to use the same boost level, then
a minimum number of board resistors can be realized by
tying together like CP[k][A,B,C] pins across all channels
k. For instance, all four CP[k][A] pins can be tied to the
same resistor running to VDD. Consequently, only three
resistors are needed to control the boost of all four
channels. If the CP Pins are tied together and the 25kΩ is
used, the value changes to a 6.25kΩ resistor because the
25kΩ is divided by 4.
Optimal Cable Boost Settings
The settable equalizing filter within the QLx4600
enables the device to optimally compensate for
frequency-dependent attenuation across a wide variety
of channels, data rates, and encoding schemes. For the
the optimal boost setting when transmitting a PRBS-7
signal. The optimal boost setting is defined as the
equalizing filter setting that minimizes the output
residual jitter of the QLx4600. The settings in Table 3
represent the optimal settings for the QLx4600C across
an ambient temperature range of 0°C to +70°C. The
optimal setting at room temperature (+20°C to +40°C)
is generally one to two settings lower than the values
listed in Table 4.
Register Description
The QLx4600-S30’s internal registers are listed in
Table 4. Register 1 determines whether the CP pins or
register values 2 through 21 are used to set the boost
level. When this register is set, the QLx4600-S30 uses
registers 2-6, 7-11, 12-16, and 17-21 to set the boost
level of equalizers 1, 2, 3, and 4. When register 1 is not
set, the CP pins are used to determine the boost level for
each equalizer channel. The use of five registers for each
equalizer channel allows all 32 boost levels as candidate
boost levels.
TABLE 3. OPTIMAL CABLE BOOST SETTINGS
CABLE
APPROX. LOSS @
2.5GHz (dB)
QLX4600-S30
BOOST
Cable A
22
10
Cable B
27
14
Cable C
35
19
NOTE: Optimal boost settings should be determined on an
application-by-application basis to account for variations in
channel type, loss characteristics, and encoding schemes. The
settings in Table 3 are presented as guidelines to be used as a
starting point for application-specific optimization.
QLx4600-S30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QLX4600SIQT7 | 功能描述:接口 - 專用 6 GBS QD CH LANE EXTENDER RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QLX4600-SL30 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Lane Extender |
| QLZ06 0012-2513 | 制造商:ebm-papst Inc 功能描述: |
| QLZ06 0018-2518 | 制造商:ebm-papst Inc 功能描述: |
| QLZ06 0600-2513 | 制造商:Ebm-Papst Industries 功能描述:Bulk |
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