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參數(shù)資料
| 型號： | QLX4600LIQSR |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER REC 6.25GBPS 46QFN |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | QLx™ |
| 應(yīng)用： | 銅電纜模塊 |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
14
FN6981.1
November 19, 2009
The boost setting for equalizer channel k can be read as
a three digit ternary number across CP[k][A,B,C]. The
ternary value is established by the value of the resistor
between VDD and the CP[k][A,B,C] pin.
As a second option, the equalizer boost setting can be
taken from a set of registers programmed through a
serial bus interface (pins 16, 17, 45, and 46). Using this
interface, a set of registers is programmed to store the
boost level. A total of 21 registers are used. Registers 2
through 21 are parsed into four 5-bit words. Each 5-bit
word determines which of 32 boost levels to use for the
corresponding equalizer. Register 1 instructs the
QLx4600-SL30 to use registers 2 through 21 to set the
boost level rather than the control pins CP[k][A,B,C].
Both options have their relative advantages. The control
pin option minimizes the need for external controllers as
the boost level can be set in the board design resulting in
a compact layout. The register option is more flexible for
cases in which the optimum boost level will not be known
and can be changed by a host bus adapter with a small
number of pins. It is noted that the serial bus interface
can also be daisy-chained among multiple QLx4600-SL30
devices to afford a compact programmable solution even
when a large number of data lines need to be equalized.
Upon power-up, the default value of all the registers (and
register 1 in particular) is zero, and thus, the CP pins are
used to set the boost level. This permits an alternate
interpretation on setting the boost level. Specifically, the
CP pins define the default boost level until the registers
are (if ever) programmed via the serial bus.
TABLE 1. DESCRIPTIONS OF PINS USED TO SET EQUALIZATION BOOST LEVEL
PIN NAME
PIN NUMBER DESCRIPTION
DI
16
Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling
the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost
setting established on CP control pins. Internally pulled down.
DO
17
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by
21 clock cycles.
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
MODE
24
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded.
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK
pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is
latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz.
Internally pulled down.
TABLE 2. MAPPING BETWEEN CP-SETTING RESISTOR
AND PROGAMMED BOOST LEVELS
RESISTANCE BETWEEN CP PIN AND VDD
SERIAL
BOOST LEVEL
CP[A]
CP[B]
CP[C]
Open
0
Open
25kΩ
2
Open
0Ω
4
Open
25kΩ
Open
6
Open
25kΩ
8
Open
25kΩ
0Ω
10
Open
0Ω
Open
12
Open
0Ω
25kΩ
14
Open
0Ω
15
0Ω
Open
16
0Ω
Open
25kΩ
17
0Ω
Open
0Ω
19
0Ω
25kΩ
Open
21
0Ω
25kΩ
23
0Ω
25kΩ
0Ω
24
0Ω
Open
26
0Ω
25kΩ
28
0Ω
31
QLx4600-SL30
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