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參數(shù)資料
| 型號： | QLX4270RIQT7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER REC 2.7GBPS 46QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QLx™ |
| 應(yīng)用： | 顯示端口 |
| 接口： | 串行 |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | QLX4270RIQT7-DKR QLX4270RIQT7-DKR-ND QLX4270RIQT7DKR |
3
FN6972.2
March 3, 2010
Pin Descriptions
PIN NAME
PIN
NUMBER
DESCRIPTION
DT
1
Detection Threshold. Reference DC CURRENT threshold for input signal power detection. Data
output Out[k] is muted when the power of the equalized version of In[k] falls below the threshold.
Tie to ground to disable electrical idle preservation and always enable the limiting amplifier.
IN1[P,N]
2, 3
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
VDD
4, 7, 10, 29,
32, 35
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
ground is recommended for each of these pins for broad high-frequency noise suppression.
IN2[P,N]
5, 6
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IN3[P,N]
8, 9
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IN4[P,N]
11, 12
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IS1
13
Impedance Select 1. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
IS2
14
Impedance Select 2. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
GND
15, 24
Ground
NC
16, 17, 45,
46
No-Connect
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
IS4
25
Impedance Select 4. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
IS3
26
Impedance Select 3. CMOS logic input. When the voltage on this pin is LOW, the single-ended input
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used
to disable some of the channels in case the DisplayPort application has less than four links, in order
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.
OUT4[N,P]
27, 28
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT3[N,P]
30, 31
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT2[N,P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT1[N,P]
36, 37
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
BGREF
38
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Exposed Pad
-
Exposed ground pad. For proper electrical and thermal performance, this pad should be connected
to the PCB ground plane.
QLx4270-DP
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