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參數(shù)資料
| 型號(hào)： | QLX111RIQT7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQCC16 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, QFN-16 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 462K |
| 代理商： | QLX111RIQT7 |
6
FN6987.0
October 26, 2009
Operation
The QLx111GRx is an advanced lane-extender for
high-speed interconnects. A functional diagram of
QLx111GRx is shown in Figure 4. In addition to a robust
equalization filter to compensate for channel loss and
restore signal fidelity, the QLx111GRx contains unique
integrated features to preserve special signaling
protocols typically broken by other equalizers. The signal
detect function is used to mute the channel output when
the equalized signal falls below the level determined by
the Detection Threshold (DT) pin voltage. This function is
intended to preserve periods of line silence (“quiescent
state” in InfiniBand contexts). Furthermore, the output of
the Signal Detect/DT comparator is used as a loss of
signal (LOS) indicator to indicate the absence of a
received signal.
As illustrated in Figure 4, the core of the high-speed
signal path in the QLx111GRx is a sophisticated equalizer
followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. The equalizer
is followed by a limiting amplification stage that provides
a clean output signal with full amplitude swing and fast
rise-fall times for reliable signal decoding in a subsequent
receiver.
Adjustable Equalization Boost
QLx111GRx features a settable equalizer for custom
signal restoration. The flexibility of this adjustable
compensation architecture enables signal fidelity to be
optimized on a channel-by-channel basis, providing
support for a wide variety of channel characteristics and
data rates ranging from 2.5Gb/s to 11.3Gb/s. Because
the boost level is externally set rather than internally
adapted, the QLx111GRx provides reliable
communication from the very first bit transmitted. There
is no time needed for adaptation and control loop
convergence. Furthermore, there are no pathological
data patterns that will cause the QLx111GRx to move to
an incorrect boost level.
Control Pin Boost Setting
The connectivity of the CP pins are used to determine the
boost level of QLx111GRx. Table 1 defines the mapping
from the 2-bit CP word to the 5 available boost levels.
CML I nput and Output Buffers
The input and output buffers for the high-speed data
channel in the QLx111GRx are implemented using CML.
Equivalent input and output circuits are shown in
Figures 6 and 7.
FI GURE 4. FUNCTI ONAL DI AGRAM OF A SI NGLE CHANNEL W I THI N THE QLx111GRx
TABLE 1. MAPPI NG BETW EEN BOOST LEVEL AND CP-
PI N CONNECTI VI TY
CP[ A]
CP[ B]
BOOST LEV EL
No Connect
No Connect
0
No Connect
Gnd
1
No Connect
VDD
2
Gnd
No Connect
3
Gnd
Gnd
4
FI GURE 5. GAI N PROFI LE FOR VARI OUS BOOST
SETTI NGS I N QLx111GRx
QLx111GRx
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