參數(shù)資料
型號(hào)： QL901M-6PS680I
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： QuickMIPS ESP Family
中文描述： QuickMIPS ESP家庭
文件頁(yè)數(shù)： 23/37頁(yè)
文件大?。?/td> 432K
代理商： QL901M-6PS680I
QL901M QuickMIPS Data Sheet Rev B
23
Figure 25: SRAM Write Waveforms
Table 22
and
Table 23
below list the synchronous and asynchronous timing for the QuickMIPS Fabric
interface port. Note the following with regards to the fabric timing:
1
2
3
fb_int is asynchronous and is synchronized inside the core.
fb_bigendian is a static signal and reflects the value on the CPU_BIGENDIAN pin.
pm_* and si_* signals are synchronous to the internal MIPS clock which is twice the hclk frequency. Because this internal
clock is not brought to the outside, these signals are considered asynchronous.
All AF_PCI_* signals are static.
4
Table 22: QuickMIPS Interface Port Synchronous Timing (to hclk)
Setup Time (Tsu)
Hold Time (Thold)
Clock-to-out Time (Tco)
hresetn
x
a
x
5.11
Fabric AHB Slave Ports
ahbs_hsel
X
X
10.73
ahbs_haddr
X
X
10.56
ahbs_htrans
X
X
11.35
ahbs_hwrite
X
X
8.32
ahbs_hsize
X
X
9.50
ahbs_hburst
X
X
9.12
ahbs_hprot
X
X
9.66
ahbs_hwdata
X
X
13.07
ahbs_hrdata
5.94
0
X
ahbs_hready_out
9.55
0
X
ahbs_hresp
10.39
0
X
Fabric AHB Master Ports
ahbm_haddr
11.94
0
X
ahbm_htrans
11.33
0
X
ahbm_hwrite
10.39
0
X
ahbm_hsize
10.58
0
X
(Sheet 1 of 2)
Internal_AHB_Clock
CS_n
ADDR[31:0]
BLS_n[3:0]
OEN_n
WEN_n
DATA[31:0]
addr
byte lane select
write data
D0
D1
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