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參數(shù)資料
| 型號： | QL6600PB516 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 165K |
| 代理商： | QL6600PB516 |
Eclipse
TM
Family Data Sheet
3
Eclipse Family Data Sheet
The Eclipse logic Supercell structure, Figure 2, is similar to the .35 mm QuickLogic logic cell with the
addition of a second register. Both registers share CLK, SET and RESET inputs. The second register has
a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly
from a dedicated input.
NOTE:
The input "PP" is not an "input" in the classical sense. It can only be tied high or low using default
links only and is used to select which path "NZ" or "PS" is used as an input to the register. All other inputs
can be connected not only to "tiehi" and "tielo" but to multiple routing channels as well.
The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-to-one
multiplexers and two D flip-flop with asynchronous SET and RESET controls. The cell has a fan-in of
30 (including register control lines) and fits a wide range of functions with up to 17 simultaneous inputs.
It has 6 outputs; 4 combinatorial and 2 registered. The high logic capacity and fan-in of the logic cell
accommodate many user functions with a single level of logic delay while other architectures require two
or more levels of delay.
QS
Figure 2: Eclipse SuperCell
Table 2: Performance Standards
Function
Description
Slowest Speed Grade
Fastest Speed Grade
Multiplexer
16:1
5 ns
2.8 ns
Parity Tree
24
6 ns
3.4 ns
36
6 ns
3.4 ns
Counter
16 bit
250 MHz
450 MHz
32 bit
250 MHz
450 MHz
FIFO
128 x 32
155 MHz
280 MHz
256 x 16
155 MHz
280 MHz
128 x 64
155 MHz
280 MHz
Clock to Out
4.5 ns
2.5 ns
System clock
200 MHz
400 MHz
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
PS
PP
QR
AZ
OZ
QZ
NZ
FZ
Q2Z
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