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參數(shù)資料
| 型號(hào)： | QL6500PT280 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 165K |
| 代理商： | QL6500PT280 |
Eclipse
TM
Family Data Sheet
9
Eclipse Family Data Sheet
5.0 Clock Networks
5.1 Global Clocks
There are 8 global clock networks in the Eclipse device family. Global clocks can drive logic cell, I/O,
and RAM registers in the device. Five global clocks will have access to a Quad Net (local clock network)
connection with a programmable connection to the register inputs.
Figure 8: Global Clock Methodology
5.2 Quad-Net Network
There are 5 Quad-Net local clock networks in each quadrant for a total of 20 in a device.
Each Quad-Net is local to a quadrant. Quad-Net is multiplexed with the clock buffer before driving the
column clock buffers.
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