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參數(shù)資料
| 型號(hào)： | QL6500PS484 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大小： | 165K |
| 代理商： | QL6500PS484 |
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www.quicklogic.com
2001 QuickLogic Corporation
Eclipse Family Data Sheet
9.0 IEEE Standard 1149.1A
The Eclipse family of devices supports IEEE standard 1149.1a. The following public instructions are
supported: BYPASS, EXTEST, and SAMPLE/PRELOAD. Two additional modes RAMWT and RAMRD
can be used to load the RAM. The pin functions will be the same as in the QuickRAM family.
Figure 11: JTAG Block Diagram
9.1 JTAG BSDL Support
BSDL-Boundary Scan Description Language
Machine-readable data for test equipment to generate testing vectors and software
BSDL files available for all device/ package combinations from QuickLogic
Extensive industry support available and ATG (Automatic Test-vector Generation)
9.2 Security fuses
There are two security links, one to disable reading from the array, the other to disable JTAG.
9.3 Flexibility fuse
The flexibility link is actually implemented as two "default" links. If the tie-low link is programmed, RAM
power up loading (from an external EPROM) is enabled, which might affect JTAG. If the tie-hi link is
programmed, RAM power-up loading (from an external EPROM) will be disabled. JTAG will work
normally, and can also be used to load the RAM.
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