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參數(shù)資料
| 型號： | QL6250 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相結(jié)合的RAM) |
| 中文描述： | Eclipse的家庭結(jié)合性能，密度，和嵌入式內(nèi)存（Eclipse的系列性能，密度和嵌入式相結(jié)合的內(nèi)存） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 258K |
| 代理商： | QL6250 |
5-11
Preliminary
Eclipse
IEEE Standard 1149.1a.
The Eclipse family of devices supports IEEE standard 1149.1a. The following public instructions are supported:
BYPASS, EXTEST, and SAMPLE/PRELOAD. Two additional modes RAMWT and RAMRD can be used to load
the RAM. The pin functions will be the same as in the QuickRAM family.
FIGURE 13. JTAG Block Diagram
JTAG BSDL Support
BSDL-Boundary Scan Description Language
Machine-readable data for test equipment to
generate testing vectors and software
BSDL files available for all device/ package
combinations from QuickLogic
Extensive industry support available and ATG
(Automatic Test-vector Generation)
I
I
I
I
Security fuses.
There are two security links, one to disable reading
from the array, the other to disable JTAG.
Flexibility fuse.
The flexibility link is actually implemented as two
"default" links. If the tie-low link is programmed,
RAM power up loading (from an external EPROM) is
enabled, which might affect JTAG. If the tie-hi link is
programmed, RAM power-up loading (from an exter-
nal EPROM) will be disabled. JTAG will work nor-
mally, and can also be used to load the RAM.
IEEE S
TANDARD
1149.1
A
.
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