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| 型號(hào)： | QL5064-75CPB484C |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁(yè)數(shù)： | 16/37頁(yè) |
| 文件大?。?/td> | 806K |
| 代理商： | QL5064-75CPB484C |
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QL5064 QuickPCI Data Sheet
18.0 PCI Back-End Interface Signals
These internal signals can interface directly to pins or to internal logic cells or RAM blocks in the
programmable logic region of the device. These signals are used to customize the device so that it can
connect to other devices on the board directly, with no glue-logic required.
Legend
“O”
Output from FPGA to PCI
“I”
Input from PCI to FPGA
Table 1: PCI Back-End Interface Signals
Symbol
I/O
Description
Clocks
pci_clk_2fpga
I
Buffered version of the PCI clock. For use in the FPGA.
user_clk
O
FPGA supplied clock used for all interface to the embedded PCI core. This
signal is required and all communication between the embedded PCI core
and the FPGA is synchronous to this clock with the exception of the DMA
arbitrary signals.
fpga_reset
I
Global reset signal from the PCI core. Active High. This signal should be
used as the global reset for the FPGA and all other supporting circuitry.
Target Interface
user_region [2:0]
I
When
target_addr_valid
is active, these signals indicate which of the
following regions are being accessed.
3’b000 BAR0
3’b001 BAR1
3’b010 BAR2
3’b011 BAR3
3’b100 BAR4
3’b101 BAR5
3’b110 Expansion ROM
3’b111 Configuration Space 0x40-0xff
user_stop
O
Active High. Stops prefetch after the current cycle.
user_be_req [7:0]
I
Active High. Byte lanes requested by PCI for all target accesses.
user_rdwr
I
When
target_addr_valid
is active, a logic ‘1’ indicates that the requested
transaction is a read. When ‘0’ the present transaction is a write.
user_addr_valid
I
Active High. Indicates that PCI is requesting a sequentially continuing
target access.
user_req
I
Active High. When active, PCI is requesting at least one piece of data to
be transferred. Deasserted after an advance generated by a read or write
from the target FIFO’s or after ‘target_user_stop’ is asserted.
user_mult
I
Active High. PCI is requesting at least 2+ pieces of data to be transferred.
user_addr_output [32:0]
I
The current address of the PCI target transaction. Incremented
automatically by a quad word when a 64-bit piece of target data is written
or read.
(Sheet 1 of 4)
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