QL5064 QuickPCI Data Sheet
Table 3: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns)Fanout
1
2
3
4
8
TSWA
WA Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
THWA
WA Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
TSWD
WD Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
THWD
WD Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
TSWE
WE Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
THWE
WE Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
TWCRD
WCLK to RD (WA=RA) [a]
5.0
5.3
5.6
5.9
7.1
Table 4: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)Fanout
a
1
2
3
4
8
TSRA
RA Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
THRA
RA Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
TSRE
RE Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
THRE
RE Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
TRCRD
RCLK to RD [b]
4.0
4.3
4.6
4.9
6.1
Table 5: RAM Cell Asynchronous Read T iming
Symbol
Parameter
Propagation Delays (ns)Fanout
1
2
3
4
8
RPDRD
RA to RD [b]
3.0
3.3
3.6
3.9
5.1