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參數(shù)資料
| 型號： | QL4090-0CG84M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| 中文描述： | 9.0萬門QuickRAM可用PLD的結(jié)合性能，密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 405K |
| 代理商： | QL4090-0CG84M |
8-
37
90,000 Usable PLD Gate QuickRAM Combining Performance, Density
and
Embedded RAM
Military QuickRAM
Rev A
Military QuickRAM
Device Highlights
High Performance and High Density
I
Up to 90,000 Usable PLD Gates with 316 I/Os
I
300 MHz 16-bit Counters, 400 MHz Datapaths, 160+
MHz FIFOs
I
0.35um four-layer metal non-volatile CMOS process for
smallest die sizes
High Speed Embedded SRAM
I
Up to 22 dual-port RAM modules, organized in user-
configurable 1,152-bit blocks
I
5ns access times, each port independently accessible
I
Fast and efficient for FIFO, RAM, and ROM functions
Easy to Use / Fast Development Cycles
I
100% routable with 100% utilization and complete
pin-out stability
I
Variable-grain logic cells provide high performance and
100% utilization
I
Comprehensive design tools include high quality Verilog/
VHDL synthesis
Advanced I/O Capabilities
I
Interfaces with both 3.3 volt and 5.0 volt devices
I
PCI compliant with 3.3V and 5.0V buses for -1/-2
speed grades
I
Full JTAG boundary scan
I
Registered I/O cells with individually controlled clocks
and output enables
Features
Total of 316 I/O pins
I
308 bi-directional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
I
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
I
Two array clock/control networks available to the logic
cell flip-flop clock, set and reset inputs - each driven by
an input-only pin
I
Six global clock/control networks available to the logic
cell F1, clock, set and reset inputs and the input and I/O
register clock, reset and enable inputs as well as the
output enable control - each driven by an input-only or
I/O pin, or any logic cell output or I/O cell feedback
High Performance
I
Input + logic cell + output total delays under 6 ns
I
Data path speeds exceeding 400 MHz
I
Counter speeds over 300 MHz
I
FIFO speeds over 160+ MHz
Military Reliability
I
Mil-STD-883 and Miil Temp Ceramic
I
Mil Temp Plastic - Guaranteed -55
°
C to 125
°
C
TABLE 1: Selector Table
D
EVICE
H
IGHLIGHTS
F
EATURES
Device
Usable
Gates
Package
Max
I/O
Qualification
Level
Supply
Voltage
QL4016
11,520 RAM Bits
8,000-
16,000
84CPGA
84PLCC
100CQFP
144CPGA
208PQFP
208CQFP
208PQFP
208CQFP
240PQFP
256CPGA
456PBGA
70
70
82
118
174
174
174
174
207
223
316
M, /883
M
M, /883
M, /883
M
M, /883
M
M, /883
M
M, /883
M
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3V
3.3V
3.3V
3.3V
3.3V
QL4036
16,128 RAM bits
16,000-
25,000
QL4090
25,344 RAM bits
36,000-
60,000
M = Military Temperature (-15 to +125 degrees C)
/888 = MIL STD 883
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL4090-0CG84M/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4090-0PB456C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA|1584-CELL|CMOS|BGA|456PIN|PLASTIC |
| QL4090-0PB456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL4090-0PG208M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4090-0PG208M/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
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