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參數資料
| 型號： | QL3025 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | pASIC3 FPGA Combining High Performance and High Density(高性能和高密度相結合的pASIC3現場可編程門陣列) |
| 中文描述： | pASIC3 FPGA的結合高性能和高密度（高性能和高密度相結合的pASIC3現場可編程門陣列） |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 239K |
| 代理商： | QL3025 |
8-23
60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density
Military Plastic pASIC 3 Family
Rev B
Military pASIC 3 - 3.3V Family
Device Highlights
High Performance and High Density
I
60,000 Usable PLD Gates with 316 I/Os
I
16-bit counter speeds over 300 MHZ, data path
speeds over 400 MHz
I
0.35um four-layer metal non-volatile CMOS
process for smallest die sizes
Easy to Use/Fast Development Cycles
I
100% routable with 100% utilization and complete
pin-out stability
I
Variable-grain logic cells provide high performance
and 100% utilization
I
Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilities
I
Interfaces with both 3.3 volt and 5.0 volt devices
I
PCI compliant with 3.3V and 5.0V buses for -1/-2
speed grades
I
Full JTAG boundary scan
I
Registered I/O cells with individually controlled
clocks and output enables
Features
Total of 180 I/O pins
I
308 bidirectional input/output pins, PCI-compliant
for 5.0 volt and 3.3 volt buses for -1/-2 speed
grades
I
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
I
Two array clock/control networks available to the
logic cell flip-flop clock, set and reset inputs - each
driven by an input-only pin
I
Up to six global clock/control networks available
to the logic cell F1, clock, set and reset inputs and
the input and I/O register clock, reset and enable
inputs as well as the output enable control - each
driven by an input-only or I/O pin, or any logic cell
output or I/O cell feedback
High Performance
I
Input + logic cell + output total delays under 6 ns
I
Data path speeds exceeding 400 MHz
I
Counter speeds over 300 MHz
TABLE 1: Selector Table
D
EVICE
H
IGHLIGHTS
F
EATURES
Device
ASIC
Gates
PLD
Gates
Package
Max
I/O
Qualification
Level
Supply
Voltage
QL3012
QL3025
QL3040
QL3060
M = Military Temperature (-55 to +125 degrees C)
8,000
16,000
24,000
36,000
12,000
25,000
40,000
60,000
84PLCC
208PQFP
208PQFP
208PQFP
68
174
174
174
M
M
M
M
3.3V
3.3V
3.3V
3.3V
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| QL30250PB256C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3025-0PB256C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL30250PB256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
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| QL30250PB256M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
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